mediatek,ufs.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/ufs/mediatek,ufs.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Mediatek Universal Flash Storage (UFS) Controller
  8
  9maintainers:
 10  - Peter Wang <peter.wang@mediatek.com>
 11  - Chaotian Jing <chaotian.jing@mediatek.com>
 12
 13properties:
 14  compatible:
 15    enum:
 16      - mediatek,mt8183-ufshci
 17      - mediatek,mt8192-ufshci
 18      - mediatek,mt8195-ufshci
 19
 20  clocks:
 21    minItems: 1
 22    maxItems: 8
 23
 24  clock-names:
 25    minItems: 1
 26    maxItems: 8
 27
 28  phys:
 29    maxItems: 1
 30
 31  reg:
 32    maxItems: 1
 33
 34  vcc-supply: true
 35
 36  mediatek,ufs-disable-mcq:
 37    $ref: /schemas/types.yaml#/definitions/flag
 38    description: The mask to disable MCQ (Multi-Circular Queue) for UFS host.
 39
 40required:
 41  - compatible
 42  - clocks
 43  - clock-names
 44  - phys
 45  - reg
 46  - vcc-supply
 47
 48unevaluatedProperties: false
 49
 50allOf:
 51  - $ref: ufs-common.yaml
 52
 53  - if:
 54      properties:
 55        compatible:
 56          contains:
 57            enum:
 58              - mediatek,mt8195-ufshci
 59    then:
 60      properties:
 61        clocks:
 62          minItems: 8
 63        clock-names:
 64          items:
 65            - const: ufs
 66            - const: ufs_aes
 67            - const: ufs_tick
 68            - const: unipro_sysclk
 69            - const: unipro_tick
 70            - const: unipro_mp_bclk
 71            - const: ufs_tx_symbol
 72            - const: ufs_mem_sub
 73    else:
 74      properties:
 75        clocks:
 76          maxItems: 1
 77        clock-names:
 78          items:
 79            - const: ufs
 80
 81examples:
 82  - |
 83    #include <dt-bindings/clock/mt8183-clk.h>
 84    #include <dt-bindings/interrupt-controller/arm-gic.h>
 85
 86    soc {
 87        #address-cells = <2>;
 88        #size-cells = <2>;
 89
 90        ufs@ff3c0000 {
 91            compatible = "mediatek,mt8183-ufshci";
 92            reg = <0 0x11270000 0 0x2300>;
 93            interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
 94            phys = <&ufsphy>;
 95
 96            clocks = <&infracfg_ao CLK_INFRA_UFS>;
 97            clock-names = "ufs";
 98            freq-table-hz = <0 0>;
 99
100            vcc-supply = <&mt_pmic_vemc_ldo_reg>;
101        };
102    };