sifive,clint.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: SiFive Core Local Interruptor
  8
  9maintainers:
 10  - Palmer Dabbelt <palmer@dabbelt.com>
 11  - Anup Patel <anup.patel@wdc.com>
 12
 13description:
 14  SiFive (and other RISC-V) SOCs include an implementation of the SiFive
 15  Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
 16  interrupts. It directly connects to the timer and inter-processor interrupt
 17  lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
 18  interrupt controller is the parent interrupt controller for CLINT device.
 19  The clock frequency of CLINT is specified via "timebase-frequency" DT
 20  property of "/cpus" DT node. The "timebase-frequency" DT property is
 21  described in Documentation/devicetree/bindings/riscv/cpus.yaml
 22
 23  T-Head C906/C910 CPU cores include an implementation of CLINT too, however
 24  their implementation lacks a memory-mapped MTIME register, thus not
 25  compatible with SiFive ones.
 26
 27properties:
 28  compatible:
 29    oneOf:
 30      - items:
 31          - enum:
 32              - canaan,k210-clint       # Canaan Kendryte K210
 33              - eswin,eic7700-clint     # ESWIN EIC7700
 34              - sifive,fu540-c000-clint # SiFive FU540
 35              - spacemit,k1-clint       # SpacemiT K1
 36              - starfive,jh7100-clint   # StarFive JH7100
 37              - starfive,jh7110-clint   # StarFive JH7110
 38              - starfive,jh8100-clint   # StarFive JH8100
 39              - tenstorrent,blackhole-clint # Tenstorrent Blackhole
 40          - const: sifive,clint0        # SiFive CLINT v0 IP block
 41      - items:
 42          - {}
 43          - const: sifive,clint2        # SiFive CLINT v2 IP block
 44        description:
 45          SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2
 46          differs from that of sifive,clint0, making them incompatible.
 47      - items:
 48          - enum:
 49              - allwinner,sun20i-d1-clint
 50              - sophgo,cv1800b-clint
 51              - sophgo,cv1812h-clint
 52              - sophgo,sg2002-clint
 53              - thead,th1520-clint
 54          - const: thead,c900-clint
 55      - items:
 56          - const: sifive,clint0
 57          - const: riscv,clint0
 58        deprecated: true
 59        description: For the QEMU virt machine only
 60
 61    description:
 62      Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"
 63      when compatible with a SiFive CLINT.  Please refer to
 64      sifive-blocks-ip-versioning.txt for details regarding the latter.
 65
 66  reg:
 67    maxItems: 1
 68
 69  interrupts-extended:
 70    minItems: 1
 71    maxItems: 4095
 72
 73  sifive,fine-ctr-bits:
 74    maximum: 15
 75    description: The width in bits of the fine counter.
 76
 77if:
 78  properties:
 79    compatible:
 80      contains:
 81        const: sifive,clint2
 82then:
 83  required:
 84    - sifive,fine-ctr-bits
 85else:
 86  properties:
 87    sifive,fine-ctr-bits: false
 88
 89additionalProperties: false
 90
 91required:
 92  - compatible
 93  - reg
 94  - interrupts-extended
 95
 96examples:
 97  - |
 98    timer@2000000 {
 99      compatible = "sifive,fu540-c000-clint", "sifive,clint0";
100      interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
101                            <&cpu2intc 3>, <&cpu2intc 7>,
102                            <&cpu3intc 3>, <&cpu3intc 7>,
103                            <&cpu4intc 3>, <&cpu4intc 7>;
104      reg = <0x2000000 0x10000>;
105    };
106...