nvidia,tegra186-timer.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: NVIDIA Tegra186 timer
  8
  9maintainers:
 10  - Thierry Reding <treding@nvidia.com>
 11
 12description: >
 13  The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
 14  counter. Each NV timer selects its timing reference signal from the 1 MHz
 15  reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be
 16  programmed to generate one-shot, periodic, or watchdog interrupts.
 17
 18properties:
 19  compatible:
 20    oneOf:
 21      - const: nvidia,tegra186-timer
 22        description: >
 23          The Tegra186 timer provides ten 29-bit timer counters.
 24      - const: nvidia,tegra234-timer
 25        description: >
 26          The Tegra234 timer provides sixteen 29-bit timer counters.
 27
 28  reg:
 29    maxItems: 1
 30
 31  interrupts: true
 32
 33allOf:
 34  - if:
 35      properties:
 36        compatible:
 37          contains:
 38            const: nvidia,tegra186-timer
 39    then:
 40      properties:
 41        interrupts:
 42          maxItems: 10
 43          description: >
 44            One per each timer channels 0 through 9.
 45
 46  - if:
 47      properties:
 48        compatible:
 49          contains:
 50            const: nvidia,tegra234-timer
 51    then:
 52      properties:
 53        interrupts:
 54          maxItems: 16
 55          description: >
 56            One per each timer channels 0 through 15.
 57
 58required:
 59  - compatible
 60  - reg
 61  - interrupts
 62
 63additionalProperties: false
 64
 65examples:
 66  - |
 67    #include <dt-bindings/interrupt-controller/arm-gic.h>
 68    #include <dt-bindings/interrupt-controller/irq.h>
 69
 70    timer@3010000 {
 71        compatible = "nvidia,tegra186-timer";
 72        reg = <0x03010000 0x000e0000>;
 73        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 74                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 75                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 76                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 77                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 78                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 79                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 80                     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 81                     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 82                     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 83    };
 84
 85  - |
 86    #include <dt-bindings/interrupt-controller/arm-gic.h>
 87    #include <dt-bindings/interrupt-controller/irq.h>
 88
 89    timer@2080000 {
 90        compatible = "nvidia,tegra234-timer";
 91        reg = <0x02080000 0x00121000>;
 92        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 93                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 94                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 95                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 96                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 97                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 98                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 99                     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
100                     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
101                     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
102                     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
103                     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
104                     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
105                     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
106                     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
107                     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
108    };