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nvidia,tegra124-soctherm.yaml
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linux-6.19.14/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/thermal/nvidia,tegra124-soctherm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra124 SOCTHERM Thermal Management System 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 13description: The SOCTHERM IP block contains thermal sensors, support for 14 polled or interrupt-based thermal monitoring, CPU and GPU throttling based 15 on temperature trip points, and handling external overcurrent notifications. 16 It is also used to manage emergency shutdown in an overheating situation. 17 18properties: 19 compatible: 20 enum: 21 - nvidia,tegra114-soctherm 22 - nvidia,tegra124-soctherm 23 - nvidia,tegra132-soctherm 24 - nvidia,tegra210-soctherm 25 - nvidia,tegra210b01-soctherm 26 27 reg: 28 maxItems: 2 29 30 reg-names: 31 maxItems: 2 32 33 interrupts: 34 items: 35 - description: module interrupt 36 - description: EDP interrupt 37 38 interrupt-names: 39 items: 40 - const: thermal 41 - const: edp 42 43 clocks: 44 items: 45 - description: thermal sensor clock 46 - description: module clock 47 48 clock-names: 49 items: 50 - const: tsensor 51 - const: soctherm 52 53 resets: 54 items: 55 - description: module reset 56 57 reset-names: 58 items: 59 - const: soctherm 60 61 "#thermal-sensor-cells": 62 const: 1 63 64 throttle-cfgs: 65 $ref: thermal-cooling-devices.yaml 66 description: A sub-node which is a container of configuration for each 67 hardware throttle events. These events can be set as cooling devices. 68 Throttle event sub-nodes must be named as "light" or "heavy". 69 unevaluatedProperties: false 70 patternProperties: 71 "^(light|heavy|oc1)$": 72 type: object 73 additionalProperties: false 74 75 properties: 76 "#cooling-cells": 77 const: 2 78 79 nvidia,priority: 80 $ref: /schemas/types.yaml#/definitions/uint32 81 minimum: 1 82 maximum: 100 83 description: Each throttles has its own throttle settings, so the 84 SW need to set priorities for various throttle, the HW arbiter 85 can select the final throttle settings. Bigger value indicates 86 higher priority, In general, higher priority translates to lower 87 target frequency. SW needs to ensure that critical thermal 88 alarms are given higher priority, and ensure that there is no 89 race if priority of two vectors is set to the same value. 90 91 nvidia,cpu-throt-percent: 92 description: This property is for Tegra124 and Tegra210. It is the 93 throttling depth of pulse skippers, it's the percentage 94 throttling. 95 minimum: 0 96 maximum: 100 97 98 nvidia,cpu-throt-level: 99 $ref: /schemas/types.yaml#/definitions/uint32 100 description: This property is only for Tegra132, it is the level 101 of pulse skippers, which used to throttle clock frequencies. It 102 indicates cpu clock throttling depth, and the depth can be 103 programmed. 104 enum: 105 # none (TEGRA_SOCTHERM_THROT_LEVEL_NONE) 106 - 0 107 # low (TEGRA_SOCTHERM_THROT_LEVEL_LOW) 108 - 1 109 # medium (TEGRA_SOCTHERM_THROT_LEVEL_MED) 110 - 2 111 # high (TEGRA_SOCTHERM_THROT_LEVEL_HIGH) 112 - 3 113 114 nvidia,gpu-throt-level: 115 $ref: /schemas/types.yaml#/definitions/uint32 116 description: This property is for Tegra124 and Tegra210. It is the 117 level of pulse skippers, which used to throttle clock 118 frequencies. It indicates gpu clock throttling depth and can be 119 programmed to any of the following values which represent a 120 throttling percentage. 121 enum: 122 # none (0%, TEGRA_SOCTHERM_THROT_LEVEL_NONE) 123 - 0 124 # low (50%, TEGRA_SOCTHERM_THROT_LEVEL_LOW) 125 - 1 126 # medium (75%, TEGRA_SOCTHERM_THROT_LEVEL_MED) 127 - 2 128 # high (85%, TEGRA_SOCTHERM_THROT_LEVEL_HIGH) 129 - 3 130 131 # optional 132 # Tegra210 specific and valid only for OCx throttle events 133 nvidia,count-threshold: 134 $ref: /schemas/types.yaml#/definitions/uint32 135 description: Specifies the number of OC events that are required 136 for triggering an interrupt. Interrupts are not triggered if the 137 property is missing. A value of 0 will interrupt on every OC 138 alarm. 139 140 nvidia,polarity-active-low: 141 $ref: /schemas/types.yaml#/definitions/flag 142 description: Configures the polarity of the OC alaram signal. If 143 present, this means assert low, otherwise assert high. 144 145 nvidia,alarm-filter: 146 $ref: /schemas/types.yaml#/definitions/uint32 147 description: Number of clocks to filter event. When the filter 148 expires (which means the OC event has not occurred for a long 149 time), the counter is cleared and filter is rearmed. 150 default: 0 151 152 nvidia,throttle-period-us: 153 description: Specifies the number of microseconds for which 154 throttling is engaged after the OC event is deasserted. 155 default: 0 156 157 # optional 158 nvidia,thermtrips: 159 $ref: /schemas/types.yaml#/definitions/uint32-matrix 160 description: | 161 When present, this property specifies the temperature at which the 162 SOCTHERM hardware will assert the thermal trigger signal to the Power 163 Management IC, which can be configured to reset or shutdown the device. 164 It is an array of pairs where each pair represents a tsensor ID followed 165 by a temperature in milli Celcius. In the absence of this property the 166 critical trip point will be used for thermtrip temperature. 167 168 Note: 169 - the "critical" type trip points will be used to set the temperature at 170 which the SOCTHERM hardware will assert a thermal trigger if the 171 "nvidia,thermtrips" property is missing. When the thermtrips property 172 is present, the breach of a critical trip point is reported back to 173 the thermal framework to implement software shutdown. 174 175 - the "hot" type trip points will be set to SOCTHERM hardware as the 176 throttle temperature. Once the temperature of this thermal zone is 177 higher than it, it will trigger the HW throttle event. 178 items: 179 items: 180 - description: sensor ID 181 oneOf: 182 - description: CPU sensor 183 const: 0 184 - description: MEM sensor 185 const: 1 186 - description: GPU sensor 187 const: 2 188 - description: PLLX sensor 189 const: 3 190 - description: temperature threshold (in millidegree Celsius) 191 192required: 193 - compatible 194 - reg 195 - reg-names 196 - interrupts 197 - interrupt-names 198 - clocks 199 - clock-names 200 - resets 201 - reset-names 202 203allOf: 204 - $ref: thermal-sensor.yaml 205 - if: 206 properties: 207 compatible: 208 contains: 209 enum: 210 - nvidia,tegra114-soctherm 211 - nvidia,tegra124-soctherm 212 - nvidia,tegra210-soctherm 213 - nvidia,tegra210b01-soctherm 214 then: 215 properties: 216 reg: 217 items: 218 - description: SOCTHERM register set 219 - description: clock and reset controller registers 220 221 reg-names: 222 items: 223 - const: soctherm-reg 224 - const: car-reg 225 226 else: 227 properties: 228 reg: 229 items: 230 - description: SOCTHERM register set 231 - description: CCROC registers 232 233 reg-names: 234 items: 235 - const: soctherm-reg 236 - const: ccroc-reg 237 238additionalProperties: false 239 240examples: 241 - | 242 #include <dt-bindings/clock/tegra124-car.h> 243 #include <dt-bindings/interrupt-controller/arm-gic.h> 244 #include <dt-bindings/thermal/tegra124-soctherm.h> 245 246 soctherm@700e2000 { 247 compatible = "nvidia,tegra124-soctherm"; 248 reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */ 249 <0x60006000 0x400>; /* CAR reg_base */ 250 reg-names = "soctherm-reg", "car-reg"; 251 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 253 interrupt-names = "thermal", "edp"; 254 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 255 <&tegra_car TEGRA124_CLK_SOC_THERM>; 256 clock-names = "tsensor", "soctherm"; 257 resets = <&tegra_car 78>; 258 reset-names = "soctherm"; 259 260 #thermal-sensor-cells = <1>; 261 262 nvidia,thermtrips = <TEGRA124_SOCTHERM_SENSOR_CPU 102500>, 263 <TEGRA124_SOCTHERM_SENSOR_GPU 103000>; 264 265 throttle-cfgs { 266 /* 267 * When the "heavy" cooling device triggered, 268 * the HW will skip cpu clock's pulse in 85% depth, 269 * skip gpu clock's pulse in 85% level 270 */ 271 heavy { 272 nvidia,priority = <100>; 273 nvidia,cpu-throt-percent = <85>; 274 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 275 276 #cooling-cells = <2>; 277 }; 278 279 /* 280 * When the "light" cooling device triggered, 281 * the HW will skip cpu clock's pulse in 50% depth, 282 * skip gpu clock's pulse in 50% level 283 */ 284 light { 285 nvidia,priority = <80>; 286 nvidia,cpu-throt-percent = <50>; 287 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_LOW>; 288 289 #cooling-cells = <2>; 290 }; 291 292 /* 293 * If these two devices are triggered in same time, the HW throttle 294 * arbiter will select the highest priority as the final throttle 295 * settings to skip cpu pulse. 296 */ 297 298 oc1 { 299 nvidia,priority = <50>; 300 nvidia,polarity-active-low; 301 nvidia,count-threshold = <100>; 302 nvidia,alarm-filter = <5100000>; 303 nvidia,throttle-period-us = <0>; 304 nvidia,cpu-throt-percent = <75>; 305 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>; 306 }; 307 }; 308 }; 309 310 # referring to Tegra132's "reg", "reg-names" and "throttle-cfgs" 311 - | 312 thermal-sensor@700e2000 { 313 compatible = "nvidia,tegra132-soctherm"; 314 reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */ 315 <0x70040000 0x200>; /* CCROC reg_base */ 316 reg-names = "soctherm-reg", "ccroc-reg"; 317 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 319 interrupt-names = "thermal", "edp"; 320 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 321 <&tegra_car TEGRA124_CLK_SOC_THERM>; 322 clock-names = "tsensor", "soctherm"; 323 resets = <&tegra_car 78>; 324 reset-names = "soctherm"; 325 #thermal-sensor-cells = <1>; 326 327 throttle-cfgs { 328 /* 329 * When the "heavy" cooling device triggered, 330 * the HW will skip cpu clock's pulse in HIGH level 331 */ 332 heavy { 333 nvidia,priority = <100>; 334 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 335 336 #cooling-cells = <2>; 337 }; 338 339 /* 340 * When the "light" cooling device triggered, 341 * the HW will skip cpu clock's pulse in MED level 342 */ 343 light { 344 nvidia,priority = <80>; 345 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>; 346 347 #cooling-cells = <2>; 348 }; 349 350 /* 351 * If these two devices are triggered in same time, the HW throttle 352 * arbiter will select the highest priority as the final throttle 353 * settings to skip cpu pulse. 354 */ 355 }; 356 }; 357 358 # referring to thermal sensors 359 - | 360 thermal-zones { 361 cpu-thermal { 362 polling-delay-passive = <1000>; 363 polling-delay = <1000>; 364 365 thermal-sensors = <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 366 367 trips { 368 cpu_shutdown_trip: shutdown-trip { 369 temperature = <102500>; 370 hysteresis = <1000>; 371 type = "critical"; 372 }; 373 374 cpu_throttle_trip: throttle-trip { 375 temperature = <100000>; 376 hysteresis = <1000>; 377 type = "hot"; 378 }; 379 }; 380 381 cooling-maps { 382 map0 { 383 trip = <&cpu_throttle_trip>; 384 cooling-device = <&throttle_heavy 1 1>; 385 }; 386 }; 387 }; 388 };
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