qcom,x1e80100-spmi-pmic-arb.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/spmi/qcom,x1e80100-spmi-pmic-arb.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm X1E80100 SPMI Controller (PMIC Arbiter v7)
  8
  9maintainers:
 10  - Stephen Boyd <sboyd@kernel.org>
 11
 12description: |
 13  The X1E80100 SPMI PMIC Arbiter implements HW version 7 and it's an SPMI
 14  controller with wrapping arbitration logic to allow for multiple on-chip
 15  devices to control up to 2 SPMI separate buses.
 16
 17  The PMIC Arbiter can also act as an interrupt controller, providing interrupts
 18  to slave devices.
 19
 20properties:
 21  compatible:
 22    oneOf:
 23      - items:
 24          - const: qcom,sar2130p-spmi-pmic-arb
 25          - const: qcom,x1e80100-spmi-pmic-arb
 26      - const: qcom,x1e80100-spmi-pmic-arb
 27
 28  reg:
 29    items:
 30      - description: core registers
 31      - description: tx-channel per virtual slave registers
 32      - description: rx-channel (called observer) per virtual slave registers
 33
 34  reg-names:
 35    items:
 36      - const: core
 37      - const: chnls
 38      - const: obsrvr
 39
 40  ranges: true
 41
 42  '#address-cells':
 43    const: 2
 44
 45  '#size-cells':
 46    const: 2
 47
 48  qcom,ee:
 49    $ref: /schemas/types.yaml#/definitions/uint32
 50    minimum: 0
 51    maximum: 5
 52    description: >
 53      indicates the active Execution Environment identifier
 54
 55  qcom,channel:
 56    $ref: /schemas/types.yaml#/definitions/uint32
 57    minimum: 0
 58    maximum: 5
 59    description: >
 60      which of the PMIC Arb provided channels to use for accesses
 61
 62patternProperties:
 63  "^spmi@[a-f0-9]+$":
 64    type: object
 65    $ref: /schemas/spmi/spmi.yaml
 66    unevaluatedProperties: false
 67
 68    properties:
 69      reg:
 70        items:
 71          - description: configuration registers
 72          - description: interrupt controller registers
 73
 74      reg-names:
 75        items:
 76          - const: cnfg
 77          - const: intr
 78
 79      interrupts:
 80        maxItems: 1
 81
 82      interrupt-names:
 83        const: periph_irq
 84
 85      interrupt-controller: true
 86
 87      '#interrupt-cells':
 88        const: 4
 89        description: |
 90          cell 1: slave ID for the requested interrupt (0-15)
 91          cell 2: peripheral ID for requested interrupt (0-255)
 92          cell 3: the requested peripheral interrupt (0-7)
 93          cell 4: interrupt flags indicating level-sense information,
 94                  as defined in dt-bindings/interrupt-controller/irq.h
 95
 96required:
 97  - compatible
 98  - reg-names
 99  - qcom,ee
100  - qcom,channel
101
102additionalProperties: false
103
104examples:
105  - |
106    #include <dt-bindings/interrupt-controller/arm-gic.h>
107
108    soc {
109      #address-cells = <2>;
110      #size-cells = <2>;
111
112      spmi: arbiter@c400000 {
113        compatible = "qcom,x1e80100-spmi-pmic-arb";
114        reg = <0 0x0c400000 0 0x3000>,
115              <0 0x0c500000 0 0x4000000>,
116              <0 0x0c440000 0 0x80000>;
117        reg-names = "core", "chnls", "obsrvr";
118
119        qcom,ee = <0>;
120        qcom,channel = <0>;
121
122        #address-cells = <2>;
123        #size-cells = <2>;
124        ranges;
125
126        spmi_bus0: spmi@c42d000 {
127          reg = <0 0x0c42d000 0 0x4000>,
128                <0 0x0c4c0000 0 0x10000>;
129          reg-names = "cnfg", "intr";
130
131          interrupt-names = "periph_irq";
132          interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
133          interrupt-controller;
134          #interrupt-cells = <4>;
135
136          #address-cells = <2>;
137          #size-cells = <0>;
138        };
139      };
140    };