st,stm32mp25-ospi.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/spi/st,stm32mp25-ospi.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: STMicroelectronics STM32 Octal Serial Peripheral Interface (OSPI)
  8
  9maintainers:
 10  - Patrice Chotard <patrice.chotard@foss.st.com>
 11
 12allOf:
 13  - $ref: spi-controller.yaml#
 14
 15properties:
 16  compatible:
 17    const: st,stm32mp25-ospi
 18
 19  reg:
 20    maxItems: 1
 21
 22  memory-region:
 23    description:
 24      Memory region to be used for memory-map read access.
 25      In memory-mapped mode, read access are performed from the memory
 26      device using the direct mapping.
 27    maxItems: 1
 28
 29  clocks:
 30    maxItems: 1
 31
 32  interrupts:
 33    maxItems: 1
 34
 35  resets:
 36    items:
 37      - description: phandle to OSPI block reset
 38      - description: phandle to delay block reset
 39
 40  dmas:
 41    maxItems: 2
 42
 43  dma-names:
 44    items:
 45      - const: tx
 46      - const: rx
 47
 48  st,syscfg-dlyb:
 49    description: configure OCTOSPI delay block.
 50    $ref: /schemas/types.yaml#/definitions/phandle-array
 51    items:
 52      - description: phandle to syscfg
 53      - description: register offset within syscfg
 54
 55  access-controllers:
 56    description: phandle to the rifsc device to check access right
 57      and in some cases, an additional phandle to the rcc device for
 58      secure clock control.
 59    items:
 60      - description: phandle to bus controller
 61      - description: phandle to clock controller
 62    minItems: 1
 63
 64  power-domains:
 65    maxItems: 1
 66
 67required:
 68  - compatible
 69  - reg
 70  - clocks
 71  - resets
 72  - interrupts
 73  - st,syscfg-dlyb
 74
 75unevaluatedProperties: false
 76
 77examples:
 78  - |
 79    #include <dt-bindings/clock/st,stm32mp25-rcc.h>
 80    #include <dt-bindings/interrupt-controller/arm-gic.h>
 81    #include <dt-bindings/reset/st,stm32mp25-rcc.h>
 82
 83    spi@40430000 {
 84      compatible = "st,stm32mp25-ospi";
 85      reg = <0x40430000 0x400>;
 86      memory-region = <&mm_ospi1>;
 87      interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 88      dmas = <&hpdma 2 0x62 0x00003121 0x0>,
 89             <&hpdma 2 0x42 0x00003112 0x0>;
 90      dma-names = "tx", "rx";
 91      clocks = <&scmi_clk CK_SCMI_OSPI1>;
 92      resets = <&scmi_reset RST_SCMI_OSPI1>, <&scmi_reset RST_SCMI_OSPI1DLL>;
 93      access-controllers = <&rifsc 74>;
 94      power-domains = <&CLUSTER_PD>;
 95      st,syscfg-dlyb = <&syscfg 0x1000>;
 96
 97      #address-cells = <1>;
 98      #size-cells = <0>;
 99
100      flash@0 {
101        compatible = "jedec,spi-nor";
102        reg = <0>;
103        spi-rx-bus-width = <4>;
104        spi-max-frequency = <108000000>;
105      };
106    };