sprd,spi-adi.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Spreadtrum ADI controller
  8
  9maintainers:
 10  - Orson Zhai <orsonzhai@gmail.com>
 11  - Baolin Wang <baolin.wang7@gmail.com>
 12  - Chunyan Zhang <zhang.lyra@gmail.com>
 13
 14description: |
 15  ADI is the abbreviation of Anolog-Digital interface, which is used to access
 16  analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
 17  framework for its hardware implementation is alike to SPI bus and its timing
 18  is compatile to SPI timing.
 19
 20  ADI controller has 50 channels including 2 software read/write channels and
 21  48 hardware channels to access analog chip. For 2 software read/write channels,
 22  users should set ADI registers to access analog chip. For hardware channels,
 23  we can configure them to allow other hardware components to use it independently,
 24  which means we can just link one analog chip address to one hardware channel,
 25  then users can access the mapped analog chip address by this hardware channel
 26  triggered by hardware components instead of ADI software channels.
 27
 28  Thus we introduce one property named "sprd,hw-channels" to configure hardware
 29  channels, the first value specifies the hardware channel id which is used to
 30  transfer data triggered by hardware automatically, and the second value specifies
 31  the analog chip address where user want to access by hardware components.
 32
 33  Since we have multi-subsystems will use unique ADI to access analog chip, when
 34  one system is reading/writing data by ADI software channels, that should be under
 35  one hardware spinlock protection to prevent other systems from reading/writing
 36  data by ADI software channels at the same time, or two parallel routine of setting
 37  ADI registers will make ADI controller registers chaos to lead incorrect results.
 38  Then we need one hardware spinlock to synchronize between the multiple subsystems.
 39
 40  The new version ADI controller supplies multiple master channels for different
 41  subsystem accessing, that means no need to add hardware spinlock to synchronize,
 42  thus change the hardware spinlock support to be optional to keep backward
 43  compatibility.
 44
 45allOf:
 46  - $ref: /schemas/spi/spi-controller.yaml#
 47
 48properties:
 49  compatible:
 50    enum:
 51      - sprd,sc9860-adi
 52      - sprd,sc9863-adi
 53      - sprd,ums512-adi
 54
 55  reg:
 56    maxItems: 1
 57
 58  hwlocks:
 59    maxItems: 1
 60
 61  hwlock-names:
 62    const: adi
 63
 64  sprd,hw-channels:
 65    $ref: /schemas/types.yaml#/definitions/uint32-matrix
 66    description: A list of hardware channels
 67    minItems: 1
 68    maxItems: 48
 69    items:
 70      items:
 71        - description: The hardware channel id which is used to transfer data
 72            triggered by hardware automatically, channel id 0-1 are for software
 73            use, 2-49 are hardware channels.
 74          minimum: 2
 75          maximum: 49
 76        - description: The analog chip address where user want to access by
 77            hardware components.
 78
 79required:
 80  - compatible
 81  - reg
 82  - '#address-cells'
 83  - '#size-cells'
 84
 85unevaluatedProperties: false
 86
 87examples:
 88  - |
 89    aon {
 90        #address-cells = <2>;
 91        #size-cells = <2>;
 92
 93        adi_bus: spi@40030000 {
 94            compatible = "sprd,sc9860-adi";
 95            reg = <0 0x40030000 0 0x10000>;
 96            hwlocks = <&hwlock1 0>;
 97            hwlock-names = "adi";
 98            #address-cells = <1>;
 99            #size-cells = <0>;
100            sprd,hw-channels = <30 0x8c20>;
101        };
102    };
103...