spi-peripheral-props.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Peripheral-specific properties for a SPI bus.
  8
  9description:
 10  Many SPI controllers need to add properties to peripheral devices. They could
 11  be common properties like spi-max-frequency, spi-cs-high, etc. or they could
 12  be controller specific like delay in clock or data lines, etc. These
 13  properties need to be defined in the peripheral node because they are
 14  per-peripheral and there can be multiple peripherals attached to a
 15  controller. All those properties are listed here. The controller specific
 16  properties should go in their own separate schema that should be referenced
 17  from here.
 18
 19maintainers:
 20  - Mark Brown <broonie@kernel.org>
 21
 22properties:
 23  reg:
 24    minItems: 1
 25    maxItems: 256
 26    items:
 27      items:
 28        - minimum: 0
 29          maximum: 256
 30    description:
 31      Chip select used by the device.
 32
 33  spi-cs-high:
 34    $ref: /schemas/types.yaml#/definitions/flag
 35    description:
 36      The device requires the chip select active high.
 37
 38  spi-lsb-first:
 39    $ref: /schemas/types.yaml#/definitions/flag
 40    description:
 41      The device requires the LSB first mode.
 42
 43  spi-max-frequency:
 44    $ref: /schemas/types.yaml#/definitions/uint32
 45    description:
 46      Maximum SPI clocking speed of the device in Hz.
 47
 48  spi-cs-setup-delay-ns:
 49    description:
 50      Delay in nanoseconds to be introduced by the controller after CS is
 51      asserted.
 52
 53  spi-cs-hold-delay-ns:
 54    description:
 55      Delay in nanoseconds to be introduced by the controller before CS is
 56      de-asserted.
 57
 58  spi-cs-inactive-delay-ns:
 59    description:
 60      Delay in nanoseconds to be introduced by the controller after CS is
 61      de-asserted.
 62
 63  spi-rx-bus-width:
 64    description:
 65      Bus width to the SPI bus used for read transfers.
 66      If 0 is provided, then no RX will be possible on this device.
 67    $ref: /schemas/types.yaml#/definitions/uint32
 68    enum: [0, 1, 2, 4, 8]
 69    default: 1
 70
 71  spi-rx-delay-us:
 72    description:
 73      Delay, in microseconds, after a read transfer.
 74
 75  rx-sample-delay-ns:
 76    description: SPI Rx sample delay offset, unit is nanoseconds.
 77      The delay from the default sample time before the actual
 78      sample of the rxd input signal occurs.
 79
 80  spi-tx-bus-width:
 81    description:
 82      Bus width to the SPI bus used for write transfers.
 83      If 0 is provided, then no TX will be possible on this device.
 84    $ref: /schemas/types.yaml#/definitions/uint32
 85    enum: [0, 1, 2, 4, 8]
 86    default: 1
 87
 88  spi-tx-delay-us:
 89    description:
 90      Delay, in microseconds, after a write transfer.
 91
 92  stacked-memories:
 93    description: Several SPI memories can be wired in stacked mode.
 94      This basically means that either a device features several chip
 95      selects, or that different devices must be seen as a single
 96      bigger chip. This basically doubles (or more) the total address
 97      space with only a single additional wire, while still needing
 98      to repeat the commands when crossing a chip boundary. The size of
 99      each chip should be provided as members of the array.
100    $ref: /schemas/types.yaml#/definitions/uint64-array
101    minItems: 2
102    maxItems: 4
103
104  parallel-memories:
105    description: Several SPI memories can be wired in parallel mode.
106      The devices are physically on a different buses but will always
107      act synchronously as each data word is spread across the
108      different memories (eg. even bits are stored in one memory, odd
109      bits in the other). This basically doubles the address space and
110      the throughput while greatly complexifying the wiring because as
111      many busses as devices must be wired. The size of each chip should
112      be provided as members of the array.
113    $ref: /schemas/types.yaml#/definitions/uint64-array
114    minItems: 2
115    maxItems: 4
116
117  st,spi-midi-ns:
118    deprecated: true
119    description: |
120      Only for STM32H7, (Master Inter-Data Idleness) minimum time
121      delay in nanoseconds inserted between two consecutive data frames.
122
123# The controller specific properties go here.
124allOf:
125  - $ref: arm,pl022-peripheral-props.yaml#
126  - $ref: cdns,qspi-nor-peripheral-props.yaml#
127  - $ref: fsl,dspi-peripheral-props.yaml#
128  - $ref: samsung,spi-peripheral-props.yaml#
129  - $ref: nvidia,tegra210-quad-peripheral-props.yaml#
130
131additionalProperties: true