FILE
qcom,spi-qpic-snand.yaml
File preview with syntax highlighting.
linux-6.19.14/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm QPIC NAND controller 8 9maintainers: 10 - Md sadre Alam <quic_mdalam@quicinc.com> 11 12description: 13 The QCOM QPIC-SPI-NAND flash controller is an extended version of 14 the QCOM QPIC NAND flash controller. It can work both in serial 15 and parallel mode. It supports typical SPI-NAND page cache 16 operations in single, dual or quad IO mode with pipelined ECC 17 encoding/decoding using the QPIC ECC HW engine. 18 19allOf: 20 - $ref: /schemas/spi/spi-controller.yaml# 21 22properties: 23 compatible: 24 oneOf: 25 - items: 26 - enum: 27 - qcom,ipq5018-snand 28 - qcom,ipq5332-snand 29 - qcom,ipq5424-snand 30 - const: qcom,ipq9574-snand 31 - const: qcom,ipq9574-snand 32 33 reg: 34 maxItems: 1 35 36 clocks: 37 maxItems: 3 38 39 clock-names: 40 items: 41 - const: core 42 - const: aon 43 - const: iom 44 45 dmas: 46 items: 47 - description: tx DMA channel 48 - description: rx DMA channel 49 - description: cmd DMA channel 50 51 dma-names: 52 items: 53 - const: tx 54 - const: rx 55 - const: cmd 56 57required: 58 - compatible 59 - reg 60 - clocks 61 - clock-names 62 63unevaluatedProperties: false 64 65examples: 66 - | 67 #include <dt-bindings/clock/qcom,ipq9574-gcc.h> 68 spi@79b0000 { 69 compatible = "qcom,ipq9574-snand"; 70 reg = <0x1ac00000 0x800>; 71 72 clocks = <&gcc GCC_QPIC_CLK>, 73 <&gcc GCC_QPIC_AHB_CLK>, 74 <&gcc GCC_QPIC_IO_MACRO_CLK>; 75 clock-names = "core", "aon", "iom"; 76 77 #address-cells = <1>; 78 #size-cells = <0>; 79 80 flash@0 { 81 compatible = "spi-nand"; 82 reg = <0>; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 nand-ecc-engine = <&qpic_nand>; 86 nand-ecc-strength = <4>; 87 nand-ecc-step-size = <512>; 88 }; 89 };
~/
Read-only file preview.