qcom,spi-geni-qcom.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/spi/qcom,spi-geni-qcom.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
  8
  9maintainers:
 10  - Andy Gross <agross@kernel.org>
 11  - Bjorn Andersson <bjorn.andersson@linaro.org>
 12  - Krzysztof Kozlowski <krzk@kernel.org>
 13
 14description:
 15  The QUP v3 core is a GENI based AHB slave that provides a common data path
 16  (an output FIFO and an input FIFO) for serial peripheral interface (SPI)
 17  mini-core.
 18
 19  SPI in master mode supports up to 50MHz, up to four chip selects,
 20  programmable data path from 4 bits to 32 bits and numerous protocol variants.
 21
 22  SPI Controller nodes must be child of GENI based Qualcomm Universal
 23  Peripharal. Please refer GENI based QUP wrapper controller node bindings
 24  described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml.
 25
 26allOf:
 27  - $ref: /schemas/spi/spi-controller.yaml#
 28  - $ref: /schemas/soc/qcom/qcom,se-common-props.yaml#
 29
 30properties:
 31  compatible:
 32    const: qcom,geni-spi
 33
 34  clocks:
 35    maxItems: 1
 36
 37  clock-names:
 38    const: se
 39
 40  dmas:
 41    maxItems: 2
 42
 43  dma-names:
 44    items:
 45      - const: tx
 46      - const: rx
 47
 48  interconnects:
 49    minItems: 2
 50    maxItems: 3
 51
 52  interconnect-names:
 53    minItems: 2
 54    items:
 55      - const: qup-core
 56      - const: qup-config
 57      - const: qup-memory
 58
 59  interrupts:
 60    maxItems: 1
 61
 62  operating-points-v2: true
 63
 64  power-domains:
 65    maxItems: 1
 66
 67  reg:
 68    maxItems: 1
 69
 70required:
 71  - compatible
 72  - clocks
 73  - clock-names
 74  - interrupts
 75  - reg
 76
 77unevaluatedProperties: false
 78
 79examples:
 80  - |
 81    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
 82    #include <dt-bindings/interconnect/qcom,sc7180.h>
 83    #include <dt-bindings/interrupt-controller/arm-gic.h>
 84    #include <dt-bindings/power/qcom-rpmpd.h>
 85
 86    spi@880000 {
 87        compatible = "qcom,geni-spi";
 88        reg = <0x00880000 0x4000>;
 89        clock-names = "se";
 90        clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 91        pinctrl-names = "default";
 92        pinctrl-0 = <&qup_spi0_default>;
 93        interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 94        #address-cells = <1>;
 95        #size-cells = <0>;
 96        power-domains = <&rpmhpd SC7180_CX>;
 97        operating-points-v2 = <&qup_opp_table>;
 98        interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 99                        <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
100        interconnect-names = "qup-core", "qup-config";
101    };
102
103  - |
104    #include <dt-bindings/dma/qcom-gpi.h>
105
106    spi@884000 {
107        compatible = "qcom,geni-spi";
108        reg = <0x00884000 0x4000>;
109        clock-names = "se";
110        clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
111        dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
112               <&gpi_dma0 1 1 QCOM_GPI_SPI>;
113        dma-names = "tx", "rx";
114        pinctrl-names = "default";
115        pinctrl-0 = <&qup_spi1_default>;
116        interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
117        #address-cells = <1>;
118        #size-cells = <0>;
119    };