microchip,mpfs-spi.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Microchip FPGA {Q,}SPI Controllers
  8
  9description:
 10  SPI and QSPI controllers on Microchip PolarFire SoC and the "soft"/
 11  fabric IP cores they are based on
 12
 13maintainers:
 14  - Conor Dooley <conor.dooley@microchip.com>
 15
 16properties:
 17  compatible:
 18    oneOf:
 19      - items:
 20          - enum:
 21              - microchip,mpfs-qspi
 22              - microchip,pic64gx-qspi
 23          - const: microchip,coreqspi-rtl-v2
 24      - enum:
 25          - microchip,coreqspi-rtl-v2 # FPGA QSPI
 26          - microchip,corespi-rtl-v5 # FPGA CoreSPI
 27          - microchip,mpfs-spi
 28      - items:
 29          - const: microchip,pic64gx-spi
 30          - const: microchip,mpfs-spi
 31
 32  reg:
 33    maxItems: 1
 34
 35  interrupts:
 36    maxItems: 1
 37
 38  clock-names:
 39    maxItems: 1
 40
 41  clocks:
 42    maxItems: 1
 43
 44  microchip,apb-datawidth:
 45    description: APB bus data width in bits.
 46    $ref: /schemas/types.yaml#/definitions/uint32
 47    enum: [8, 16, 32]
 48    default: 8
 49
 50  microchip,frame-size:
 51    description: |
 52      Number of bits per SPI frame, as configured in Libero.
 53      In Motorola and TI modes, this corresponds directly
 54      to the requested frame size. For NSC mode this is set
 55      to 9 + the required data frame size.
 56    $ref: /schemas/types.yaml#/definitions/uint32
 57    minimum: 4
 58    maximum: 32
 59    default: 8
 60
 61  microchip,protocol-configuration:
 62    description: CoreSPI protocol selection. Determines operating mode
 63    $ref: /schemas/types.yaml#/definitions/string
 64    enum:
 65      - motorola
 66      - ti
 67      - nsc
 68    default: motorola
 69
 70  microchip,motorola-mode:
 71    description: Motorola SPI mode selection
 72    $ref: /schemas/types.yaml#/definitions/uint32
 73    enum: [0, 1, 2, 3]
 74    default: 3
 75
 76  microchip,ssel-active:
 77    description: |
 78      Keep SSEL asserted between frames when using the Motorola protocol.
 79      When present, the controller keeps SSEL active across contiguous
 80      transfers and deasserts only when the overall transfer completes.
 81    type: boolean
 82
 83required:
 84  - compatible
 85  - reg
 86  - interrupts
 87  - clocks
 88
 89allOf:
 90  - $ref: spi-controller.yaml#
 91
 92  - if:
 93      properties:
 94        compatible:
 95          contains:
 96            const: microchip,mpfs-spi
 97    then:
 98      properties:
 99        num-cs:
100          default: 1
101
102  - if:
103      properties:
104        compatible:
105          contains:
106            const: microchip,mpfs-spi
107      not:
108        required:
109          - cs-gpios
110    then:
111      properties:
112        num-cs:
113          maximum: 1
114
115  - if:
116      properties:
117        compatible:
118          contains:
119            const: microchip,corespi-rtl-v5
120    then:
121      properties:
122        num-cs:
123          minimum: 1
124          maximum: 8
125          default: 8
126
127        fifo-depth:
128          minimum: 1
129          maximum: 32
130          default: 4
131
132    else:
133      properties:
134        microchip,apb-datawidth: false
135        microchip,frame-size: false
136        microchip,protocol-configuration: false
137        microchip,motorola-mode: false
138        microchip,ssel-active: false
139
140unevaluatedProperties: false
141
142examples:
143  - |
144    #include "dt-bindings/clock/microchip,mpfs-clock.h"
145    spi@20108000 {
146        compatible = "microchip,mpfs-spi";
147        reg = <0x20108000 0x1000>;
148        clocks = <&clkcfg CLK_SPI0>;
149        interrupt-parent = <&plic>;
150        interrupts = <54>;
151    };
152...