marvell,orion-spi.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/spi/marvell,orion-spi.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Marvell Orion SPI controller
  8
  9maintainers:
 10  - Andrew Lunn <andrew@lunn.ch>
 11  - Gregory CLEMENT <gregory.clement@bootlin.com>
 12
 13allOf:
 14  - $ref: /schemas/spi/spi-controller.yaml#
 15
 16properties:
 17  compatible:
 18    oneOf:
 19      - enum:
 20          - marvell,orion-spi
 21          - marvell,armada-380-spi  # For ap80x and cp11x
 22      - items:
 23          - enum:
 24              - marvell,armada-370-spi
 25              - marvell,armada-375-spi
 26              - marvell,armada-380-spi
 27              - marvell,armada-390-spi
 28              - marvell,armada-xp-spi
 29          - const: marvell,orion-spi
 30
 31  cell-index:
 32    description: Instance id for the SPI controller
 33    deprecated: true
 34
 35  reg:
 36    minItems: 1
 37    items:
 38      - description: control registers
 39      - description: CS0 MBUS target/attribute registers for direct mode
 40      - description: CS1 MBUS target/attribute registers for direct mode
 41      - description: CS2 MBUS target/attribute registers for direct mode
 42      - description: CS3 MBUS target/attribute registers for direct mode
 43      - description: CS4 MBUS target/attribute registers for direct mode
 44      - description: CS5 MBUS target/attribute registers for direct mode
 45      - description: CS6 MBUS target/attribute registers for direct mode
 46      - description: CS7 MBUS target/attribute registers for direct mode
 47
 48  clocks:
 49    minItems: 1
 50    maxItems: 2
 51
 52  clock-names:
 53    items:
 54      - const: core
 55      - const: axi
 56
 57  interrupts:
 58    maxItems: 1
 59
 60required:
 61  - compatible
 62  - reg
 63  - clocks
 64
 65unevaluatedProperties: false
 66
 67examples:
 68  - |
 69    spi@10600 {
 70      compatible = "marvell,orion-spi";
 71      #address-cells = <1>;
 72      #size-cells = <0>;
 73      cell-index = <0>;
 74      reg = <0x10600 0x28>;
 75      clocks = <&coreclk 0>;
 76      interrupts = <23>;
 77    };
 78  - |
 79    #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
 80
 81    bus {
 82        #address-cells = <2>;
 83        #size-cells = <1>;
 84
 85        spi@10600 {
 86          compatible = "marvell,orion-spi";
 87          #address-cells = <1>;
 88          #size-cells = <0>;
 89          cell-index = <0>;
 90          reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
 91                <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
 92                <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
 93                <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
 94                <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
 95                <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
 96                <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
 97                <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
 98                <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
 99          clocks = <&coreclk 0>;
100          interrupts = <23>;
101        };
102    };