fsl,dspi.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/spi/fsl,dspi.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: ARM Freescale DSPI controller
  8
  9maintainers:
 10  - Frank Li <Frank.Li@nxp.com>
 11
 12properties:
 13  compatible:
 14    oneOf:
 15      - enum:
 16          - fsl,vf610-dspi
 17          - fsl,ls1021a-v1.0-dspi
 18          - fsl,ls1012a-dspi
 19          - fsl,ls1028a-dspi
 20          - fsl,ls1043a-dspi
 21          - fsl,ls1046a-dspi
 22          - fsl,ls1088a-dspi
 23          - fsl,ls2080a-dspi
 24          - fsl,ls2085a-dspi
 25          - fsl,lx2160a-dspi
 26          - nxp,s32g2-dspi
 27      - items:
 28          - enum:
 29              - fsl,ls1012a-dspi
 30              - fsl,ls1028a-dspi
 31              - fsl,ls1043a-dspi
 32              - fsl,ls1046a-dspi
 33              - fsl,ls1088a-dspi
 34          - const: fsl,ls1021a-v1.0-dspi
 35      - items:
 36          - const: fsl,ls2080a-dspi
 37          - const: fsl,ls2085a-dspi
 38      - items:
 39          - const: fsl,lx2160a-dspi
 40          - const: fsl,ls2085a-dspi
 41      - items:
 42          - const: nxp,s32g3-dspi
 43          - const: nxp,s32g2-dspi
 44
 45  reg:
 46    maxItems: 1
 47
 48  interrupts:
 49    maxItems: 1
 50
 51  clocks:
 52    maxItems: 1
 53
 54  clock-names:
 55    items:
 56      - const: dspi
 57
 58  dmas:
 59    items:
 60      - description: DMA controller phandle and request line for TX
 61      - description: DMA controller phandle and request line for RX
 62
 63  dma-names:
 64    items:
 65      - const: tx
 66      - const: rx
 67
 68  spi-num-chipselects:
 69    $ref: /schemas/types.yaml#/definitions/uint32
 70    description:
 71      The number of the chip native chipselect signals.
 72      cs-gpios don't count against this number.
 73
 74  big-endian: true
 75
 76  bus-num:
 77    $ref: /schemas/types.yaml#/definitions/uint32
 78    description: SoC-specific identifier for the SPI controller.
 79
 80required:
 81  - compatible
 82  - reg
 83  - clocks
 84  - clock-names
 85  - spi-num-chipselects
 86
 87allOf:
 88  - $ref: spi-controller.yaml#
 89
 90unevaluatedProperties: false
 91
 92examples:
 93  - |
 94    #include <dt-bindings/interrupt-controller/arm-gic.h>
 95    #include <dt-bindings/clock/vf610-clock.h>
 96
 97    spi@4002c000 {
 98        compatible = "fsl,vf610-dspi";
 99        reg = <0x4002c000 0x1000>;
100        #address-cells = <1>;
101        #size-cells = <0>;
102        interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
103        clocks = <&clks VF610_CLK_DSPI0>;
104        clock-names = "dspi";
105        spi-num-chipselects = <5>;
106        bus-num = <0>;
107        pinctrl-names = "default";
108        pinctrl-0 = <&pinctrl_dspi0_1>;
109        big-endian;
110
111        flash@0 {
112            compatible = "jedec,spi-nor";
113            reg = <0>;
114            spi-max-frequency = <16000000>;
115            spi-cpol;
116            spi-cpha;
117            spi-cs-setup-delay-ns = <100>;
118            spi-cs-hold-delay-ns = <50>;
119        };
120    };
121  # S32G3 in target mode
122  - |
123    spi@401d4000 {
124        compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
125        reg = <0x401d4000 0x1000>;
126        interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
127        clocks = <&clks 26>;
128        clock-names = "dspi";
129        spi-num-chipselects = <8>;
130        bus-num = <0>;
131        dmas = <&edma0 0 7>, <&edma0 0 8>;
132        dma-names = "tx", "rx";
133        spi-slave;
134    };