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qcom,wcd937x-sdw.yaml

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linux-6.19.14/Documentation/devicetree/bindings/sound/qcom,wcd937x-sdw.yaml YAML
  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/sound/qcom,wcd937x-sdw.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm SoundWire Slave devices on WCD9370/WCD9375
  8
  9maintainers:
 10  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
 11
 12description: |
 13  Qualcomm WCD9370/WCD9375 Codec is a standalone Hi-Fi audio codec IC.
 14  It has RX and TX Soundwire slave devices. This bindings is for the
 15  slave devices.
 16
 17properties:
 18  compatible:
 19    const: sdw20217010a00
 20
 21  reg:
 22    maxItems: 1
 23
 24  qcom,tx-port-mapping:
 25    description: |
 26      Specifies static port mapping between device and host tx ports.
 27      In the order of the device port index which are adc1_port, adc23_port,
 28      dmic03_mbhc_port, dmic46_port.
 29      Supports maximum 4 tx soundwire ports.
 30
 31      WCD9370 TX Port 1 (ADC1)               <=> SWR2 Port 2
 32      WCD9370 TX Port 2 (ADC2, 3)            <=> SWR2 Port 2
 33      WCD9370 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3
 34      WCD9370 TX Port 4 (DMIC4,5,6,7)        <=> SWR2 Port 4
 35
 36    $ref: /schemas/types.yaml#/definitions/uint32-array
 37    minItems: 4
 38    maxItems: 4
 39    items:
 40      enum: [1, 2, 3, 4]
 41
 42  qcom,rx-port-mapping:
 43    description: |
 44      Specifies static port mapping between device and host rx ports.
 45      In the order of device port index which are hph_port, clsh_port,
 46      comp_port, lo_port, dsd port.
 47      Supports maximum 5 rx soundwire ports.
 48
 49      WCD9370 RX Port 1 (HPH_L/R)       <==>    SWR1 Port 1 (HPH_L/R)
 50      WCD9370 RX Port 2 (CLSH)          <==>    SWR1 Port 2 (CLSH)
 51      WCD9370 RX Port 3 (COMP_L/R)      <==>    SWR1 Port 3 (COMP_L/R)
 52      WCD9370 RX Port 4 (LO)            <==>    SWR1 Port 4 (LO)
 53      WCD9370 RX Port 5 (DSD_L/R)       <==>    SWR1 Port 5 (DSD)
 54
 55    $ref: /schemas/types.yaml#/definitions/uint32-array
 56    minItems: 5
 57    maxItems: 5
 58    items:
 59      enum: [1, 2, 3, 4, 5]
 60
 61  qcom,tx-channel-mapping:
 62    description: |
 63      Specifies static channel mapping between slave and master tx port
 64      channels.
 65      In the order of slave port channels which is adc1, adc2, adc3,
 66      dmic0, dmic1, mbhc, dmic2, dmic3, dmci4, dmic5, dmic6, dmic7.
 67    $ref: /schemas/types.yaml#/definitions/uint8-array
 68    minItems: 12
 69    maxItems: 12
 70    additionalItems: false
 71    items:
 72      enum:
 73        - 1  # WCD9370_SWRM_CH1
 74        - 2  # WCD9370_SWRM_CH2
 75        - 3  # WCD9370_SWRM_CH3
 76        - 4  # WCD9370_SWRM_CH4
 77
 78  qcom,rx-channel-mapping:
 79    description: |
 80      Specifies static channels mapping between slave and master rx port
 81      channels.
 82      In the order of slave port channels, which is
 83      hph_l, hph_r, clsh, comp_l, comp_r, lo, dsd_r, dsd_l.
 84    $ref: /schemas/types.yaml#/definitions/uint8-array
 85    minItems: 8
 86    maxItems: 8
 87    additionalItems: false
 88    items:
 89      enum:
 90        - 1  # WCD9370_SWRM_CH1
 91        - 2  # WCD9370_SWRM_CH2
 92        - 3  # WCD9370_SWRM_CH3
 93        - 4  # WCD9370_SWRM_CH4
 94
 95required:
 96  - compatible
 97  - reg
 98
 99additionalProperties: false
100
101examples:
102  - |
103    soundwire@3210000 {
104        reg = <0x03210000 0x2000>;
105        #address-cells = <2>;
106        #size-cells = <0>;
107        wcd937x_rx: codec@0,4 {
108            compatible = "sdw20217010a00";
109            reg = <0 4>;
110            qcom,rx-port-mapping = <1 2 3 4 5>;
111            qcom,rx-channel-mapping = /bits/ 8 <1 2 1 1 2 1 1 2>;
112        };
113    };
114
115    soundwire@3230000 {
116        reg = <0x03230000 0x2000>;
117        #address-cells = <2>;
118        #size-cells = <0>;
119        wcd937x_tx: codec@0,3 {
120            compatible = "sdw20217010a00";
121            reg = <0 3>;
122            qcom,tx-port-mapping = <2 2 3 4>;
123            qcom,tx-channel-mapping = /bits/ 8 <1 2 1 1 2 3 3 4 1 2 3 4>;
124        };
125    };
126
127...
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