mt8195-afe-pcm.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/sound/mt8195-afe-pcm.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Mediatek AFE PCM controller for mt8195
  8
  9maintainers:
 10  - Trevor Wu <trevor.wu@mediatek.com>
 11
 12properties:
 13  compatible:
 14    const: mediatek,mt8195-audio
 15
 16  reg:
 17    maxItems: 1
 18
 19  interrupts:
 20    maxItems: 1
 21
 22  resets:
 23    maxItems: 1
 24
 25  reset-names:
 26    const: audiosys
 27
 28  memory-region:
 29    maxItems: 1
 30    description: |
 31      Shared memory region for AFE memif.  A "shared-dma-pool".
 32      See ../reserved-memory/reserved-memory.txt for details.
 33
 34  mediatek,topckgen:
 35    $ref: /schemas/types.yaml#/definitions/phandle
 36    description: The phandle of the mediatek topckgen controller
 37
 38  power-domains:
 39    maxItems: 1
 40
 41  clocks:
 42    items:
 43      - description: 26M clock
 44      - description: audio pll1 clock
 45      - description: audio pll2 clock
 46      - description: clock divider for i2si1_mck
 47      - description: clock divider for i2si2_mck
 48      - description: clock divider for i2so1_mck
 49      - description: clock divider for i2so2_mck
 50      - description: clock divider for dptx_mck
 51      - description: a1sys hoping clock
 52      - description: audio intbus clock
 53      - description: audio hires clock
 54      - description: audio local bus clock
 55      - description: mux for dptx_mck
 56      - description: mux for i2so1_mck
 57      - description: mux for i2so2_mck
 58      - description: mux for i2si1_mck
 59      - description: mux for i2si2_mck
 60      - description: audio infra 26M clock
 61      - description: infra bus clock
 62
 63  clock-names:
 64    items:
 65      - const: clk26m
 66      - const: apll1_ck
 67      - const: apll2_ck
 68      - const: apll12_div0
 69      - const: apll12_div1
 70      - const: apll12_div2
 71      - const: apll12_div3
 72      - const: apll12_div9
 73      - const: a1sys_hp_sel
 74      - const: aud_intbus_sel
 75      - const: audio_h_sel
 76      - const: audio_local_bus_sel
 77      - const: dptx_m_sel
 78      - const: i2so1_m_sel
 79      - const: i2so2_m_sel
 80      - const: i2si1_m_sel
 81      - const: i2si2_m_sel
 82      - const: infra_ao_audio_26m_b
 83      - const: scp_adsp_audiodsp
 84
 85  mediatek,etdm-in1-chn-disabled:
 86    $ref: /schemas/types.yaml#/definitions/uint8-array
 87    maxItems: 24
 88    description: Specify which input channel should be disabled.
 89
 90  mediatek,etdm-in2-chn-disabled:
 91    $ref: /schemas/types.yaml#/definitions/uint8-array
 92    maxItems: 16
 93    description: Specify which input channel should be disabled.
 94
 95patternProperties:
 96  "^mediatek,etdm-in[1-2]-mclk-always-on-rate-hz$":
 97    description: Specify etdm in mclk output rate for always on case.
 98
 99  "^mediatek,etdm-out[1-3]-mclk-always-on-rate-hz$":
100    description: Specify etdm out mclk output rate for always on case.
101
102  "^mediatek,etdm-in[1-2]-multi-pin-mode$":
103    type: boolean
104    description: if present, the etdm data mode is I2S.
105
106  "^mediatek,etdm-out[1-3]-multi-pin-mode$":
107    type: boolean
108    description: if present, the etdm data mode is I2S.
109
110  "^mediatek,etdm-in[1-2]-cowork-source$":
111    $ref: /schemas/types.yaml#/definitions/uint32
112    description: |
113      etdm modules can share the same external clock pin. Specify
114      which etdm clock source is required by this etdm in module.
115    enum:
116      - 0 # etdm1_in
117      - 1 # etdm2_in
118      - 2 # etdm1_out
119      - 3 # etdm2_out
120
121  "^mediatek,etdm-out[1-2]-cowork-source$":
122    $ref: /schemas/types.yaml#/definitions/uint32
123    description: |
124      etdm modules can share the same external clock pin. Specify
125      which etdm clock source is required by this etdm out module.
126    enum:
127      - 0 # etdm1_in
128      - 1 # etdm2_in
129      - 2 # etdm1_out
130      - 3 # etdm2_out
131
132required:
133  - compatible
134  - reg
135  - interrupts
136  - resets
137  - reset-names
138  - mediatek,topckgen
139  - power-domains
140  - clocks
141  - clock-names
142  - memory-region
143
144additionalProperties: false
145
146examples:
147  - |
148    #include <dt-bindings/interrupt-controller/arm-gic.h>
149    #include <dt-bindings/interrupt-controller/irq.h>
150
151    afe: mt8195-afe-pcm@10890000 {
152        compatible = "mediatek,mt8195-audio";
153        reg = <0x10890000 0x10000>;
154        interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
155        resets = <&watchdog 14>;
156        reset-names = "audiosys";
157        mediatek,topckgen = <&topckgen>;
158        power-domains = <&spm 7>; //MT8195_POWER_DOMAIN_AUDIO
159        memory-region = <&snd_dma_mem_reserved>;
160        clocks = <&clk26m>,
161                 <&topckgen 163>, //CLK_TOP_APLL1
162                 <&topckgen 166>, //CLK_TOP_APLL2
163                 <&topckgen 233>, //CLK_TOP_APLL12_DIV0
164                 <&topckgen 234>, //CLK_TOP_APLL12_DIV1
165                 <&topckgen 235>, //CLK_TOP_APLL12_DIV2
166                 <&topckgen 236>, //CLK_TOP_APLL12_DIV3
167                 <&topckgen 238>, //CLK_TOP_APLL12_DIV9
168                 <&topckgen 100>, //CLK_TOP_A1SYS_HP_SEL
169                 <&topckgen 33>, //CLK_TOP_AUD_INTBUS_SEL
170                 <&topckgen 34>, //CLK_TOP_AUDIO_H_SEL
171                 <&topckgen 107>, //CLK_TOP_AUDIO_LOCAL_BUS_SEL
172                 <&topckgen 98>, //CLK_TOP_DPTX_M_SEL
173                 <&topckgen 94>, //CLK_TOP_I2SO1_M_SEL
174                 <&topckgen 95>, //CLK_TOP_I2SO2_M_SEL
175                 <&topckgen 96>, //CLK_TOP_I2SI1_M_SEL
176                 <&topckgen 97>, //CLK_TOP_I2SI2_M_SEL
177                 <&infracfg_ao 50>, //CLK_INFRA_AO_AUDIO_26M_B
178                 <&scp_adsp 0>; //CLK_SCP_ADSP_AUDIODSP
179        clock-names = "clk26m",
180                      "apll1_ck",
181                      "apll2_ck",
182                      "apll12_div0",
183                      "apll12_div1",
184                      "apll12_div2",
185                      "apll12_div3",
186                      "apll12_div9",
187                      "a1sys_hp_sel",
188                      "aud_intbus_sel",
189                      "audio_h_sel",
190                      "audio_local_bus_sel",
191                      "dptx_m_sel",
192                      "i2so1_m_sel",
193                      "i2so2_m_sel",
194                      "i2si1_m_sel",
195                      "i2si2_m_sel",
196                      "infra_ao_audio_26m_b",
197                      "scp_adsp_audiodsp";
198    };
199
200...