mediatek,mt7986-afe.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/sound/mediatek,mt7986-afe.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: MediaTek AFE PCM controller for MT7986
  8
  9maintainers:
 10  - Maso Huang <maso.huang@mediatek.com>
 11
 12properties:
 13  compatible:
 14    oneOf:
 15      - const: mediatek,mt7986-afe
 16      - items:
 17          - enum:
 18              - mediatek,mt7981-afe
 19              - mediatek,mt7988-afe
 20          - const: mediatek,mt7986-afe
 21
 22  reg:
 23    maxItems: 1
 24
 25  interrupts:
 26    maxItems: 1
 27
 28  clocks:
 29    minItems: 5
 30    items:
 31      - description: audio bus clock
 32      - description: audio 26M clock
 33      - description: audio intbus clock
 34      - description: audio hopping clock
 35      - description: audio pll clock
 36      - description: mux for pcm_mck
 37      - description: audio i2s/pcm mck
 38
 39  clock-names:
 40    minItems: 5
 41    items:
 42      - const: bus_ck
 43      - const: 26m_ck
 44      - const: l_ck
 45      - const: aud_ck
 46      - const: eg2_ck
 47      - const: sel
 48      - const: i2s_m
 49
 50required:
 51  - compatible
 52  - reg
 53  - interrupts
 54  - clocks
 55  - clock-names
 56
 57allOf:
 58  - if:
 59      properties:
 60        compatible:
 61          contains:
 62            const: mediatek,mt7986-afe
 63    then:
 64      properties:
 65        clocks:
 66          items:
 67            - description: audio bus clock
 68            - description: audio 26M clock
 69            - description: audio intbus clock
 70            - description: audio hopping clock
 71            - description: audio pll clock
 72        clock-names:
 73          items:
 74            - const: bus_ck
 75            - const: 26m_ck
 76            - const: l_ck
 77            - const: aud_ck
 78            - const: eg2_ck
 79
 80  - if:
 81      properties:
 82        compatible:
 83          contains:
 84            const: mediatek,mt7981-afe
 85    then:
 86      properties:
 87        clocks:
 88          items:
 89            - description: audio bus clock
 90            - description: audio 26M clock
 91            - description: audio intbus clock
 92            - description: audio hopping clock
 93            - description: audio pll clock
 94            - description: mux for pcm_mck
 95        clock-names:
 96          items:
 97            - const: bus_ck
 98            - const: 26m_ck
 99            - const: l_ck
100            - const: aud_ck
101            - const: eg2_ck
102            - const: sel
103
104  - if:
105      properties:
106        compatible:
107          contains:
108            const: mediatek,mt7988-afe
109    then:
110      properties:
111        clocks:
112          items:
113            - description: audio bus clock
114            - description: audio 26M clock
115            - description: audio intbus clock
116            - description: audio hopping clock
117            - description: audio pll clock
118            - description: mux for pcm_mck
119            - description: audio i2s/pcm mck
120        clock-names:
121          items:
122            - const: bus_ck
123            - const: 26m_ck
124            - const: l_ck
125            - const: aud_ck
126            - const: eg2_ck
127            - const: sel
128            - const: i2s_m
129
130additionalProperties: false
131
132examples:
133  - |
134    #include <dt-bindings/interrupt-controller/arm-gic.h>
135    #include <dt-bindings/interrupt-controller/irq.h>
136    #include <dt-bindings/clock/mt7986-clk.h>
137
138    afe@11210000 {
139        compatible = "mediatek,mt7986-afe";
140        reg = <0x11210000 0x9000>;
141        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
142        clocks = <&infracfg_ao CLK_INFRA_AUD_BUS_CK>,
143                 <&infracfg_ao CLK_INFRA_AUD_26M_CK>,
144                 <&infracfg_ao CLK_INFRA_AUD_L_CK>,
145                 <&infracfg_ao CLK_INFRA_AUD_AUD_CK>,
146                 <&infracfg_ao CLK_INFRA_AUD_EG2_CK>;
147        clock-names = "bus_ck",
148                      "26m_ck",
149                      "l_ck",
150                      "aud_ck",
151                      "eg2_ck";
152        assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>,
153                          <&topckgen CLK_TOP_AUD_L_SEL>,
154                          <&topckgen CLK_TOP_A_TUNER_SEL>;
155        assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,
156                                 <&apmixedsys CLK_APMIXED_APLL2>,
157                                 <&topckgen CLK_TOP_APLL2_D4>;
158    };
159
160...