fsl,ssi.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/sound/fsl,ssi.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Freescale Synchronous Serial Interface
  8
  9maintainers:
 10  - Shengjiu Wang <shengjiu.wang@nxp.com>
 11
 12description:
 13  Notes on fsl,playback-dma and fsl,capture-dma
 14  On SOCs that have an SSI, specific DMA channels are hard-wired for playback
 15  and capture.  On the MPC8610, for example, SSI1 must use DMA channel 0 for
 16  playback and DMA channel 1 for capture.  SSI2 must use DMA channel 2 for
 17  playback and DMA channel 3 for capture.  The developer can choose which
 18  DMA controller to use, but the channels themselves are hard-wired.  The
 19  purpose of these two properties is to represent this hardware design.
 20
 21  The device tree nodes for the DMA channels that are referenced by
 22  "fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
 23  "fsl,ssi-dma-channel".  The SOC-specific compatible string (e.g.
 24  "fsl,mpc8610-dma-channel") can remain.  If these nodes are left as
 25  "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA
 26  drivers (fsldma) will attempt to use them, and it will conflict with the
 27  sound drivers.
 28
 29properties:
 30  compatible:
 31    oneOf:
 32      - items:
 33          - enum:
 34              - fsl,imx50-ssi
 35              - fsl,imx53-ssi
 36          - const: fsl,imx51-ssi
 37          - const: fsl,imx21-ssi
 38      - items:
 39          - enum:
 40              - fsl,imx25-ssi
 41              - fsl,imx27-ssi
 42              - fsl,imx35-ssi
 43              - fsl,imx51-ssi
 44          - const: fsl,imx21-ssi
 45      - items:
 46          - enum:
 47              - fsl,imx6q-ssi
 48              - fsl,imx6sl-ssi
 49              - fsl,imx6sx-ssi
 50          - const: fsl,imx51-ssi
 51      - items:
 52          - const: fsl,imx21-ssi
 53      - items:
 54          - const: fsl,mpc8610-ssi
 55
 56  reg:
 57    maxItems: 1
 58
 59  interrupts:
 60    maxItems: 1
 61
 62  clocks:
 63    items:
 64      - description: The ipg clock for register access
 65      - description: clock for SSI master mode
 66    minItems: 1
 67
 68  clock-names:
 69    items:
 70      - const: ipg
 71      - const: baud
 72    minItems: 1
 73
 74  dmas:
 75    oneOf:
 76      - items:
 77          - description: DMA controller phandle and request line for RX
 78          - description: DMA controller phandle and request line for TX
 79      - items:
 80          - description: DMA controller phandle and request line for RX0
 81          - description: DMA controller phandle and request line for TX0
 82          - description: DMA controller phandle and request line for RX1
 83          - description: DMA controller phandle and request line for TX1
 84
 85  dma-names:
 86    oneOf:
 87      - items:
 88          - const: rx
 89          - const: tx
 90      - items:
 91          - const: rx0
 92          - const: tx0
 93          - const: rx1
 94          - const: tx1
 95
 96  "#sound-dai-cells":
 97    const: 0
 98    description: optional, some dts node didn't add it.
 99
100  cell-index:
101    $ref: /schemas/types.yaml#/definitions/uint32
102    enum: [0, 1, 2]
103    description: The SSI index
104
105  ac97-gpios:
106    $ref: /schemas/types.yaml#/definitions/phandle-array
107    description: Please refer to soc-ac97link.txt
108
109  codec-handle:
110    $ref: /schemas/types.yaml#/definitions/phandle
111    description:
112      Phandle to a 'codec' node that defines an audio
113      codec connected to this SSI.  This node is typically
114      a child of an I2C or other control node.
115
116  fsl,fifo-depth:
117    $ref: /schemas/types.yaml#/definitions/uint32
118    description:
119      The number of elements in the transmit and receive FIFOs.
120      This number is the maximum allowed value for SFCSR[TFWM0].
121    enum: [8, 15]
122
123  fsl,fiq-stream-filter:
124    type: boolean
125    description:
126      Disabled DMA and use FIQ instead to filter the codec stream.
127      This is necessary for some boards where an incompatible codec
128      is connected to this SSI, e.g. on pca100 and pcm043.
129
130  fsl,mode:
131    $ref: /schemas/types.yaml#/definitions/string
132    enum: [ ac97-slave, ac97-master, i2s-slave, i2s-master,
133            lj-slave, lj-master, rj-slave, rj-master ]
134    description: |
135      "ac97-slave" - AC97 mode, SSI is clock slave
136      "ac97-master" - AC97 mode, SSI is clock master
137      "i2s-slave" - I2S mode, SSI is clock slave
138      "i2s-master" - I2S mode, SSI is clock master
139      "lj-slave" - Left justified mode, SSI is clock slave
140      "lj-master" - Left justified mode, SSI is clock master
141      "rj-slave" - Right justified mode, SSI is clock slave
142      "rj-master" - Right justified mode, SSI is clock master
143
144  fsl,ssi-asynchronous:
145    type: boolean
146    description: If specified, the SSI is to be programmed in asynchronous
147      mode.  In this mode, pins SRCK, STCK, SRFS, and STFS must
148      all be connected to valid signals.  In synchronous mode,
149      SRCK and SRFS are ignored.  Asynchronous mode allows
150      playback and capture to use different sample sizes and
151      sample rates.  Some drivers may require that SRCK and STCK
152      be connected together, and SRFS and STFS be connected
153      together.  This would still allow different sample sizes,
154      but not different sample rates.
155
156  fsl,playback-dma:
157    $ref: /schemas/types.yaml#/definitions/phandle
158    description: Phandle to a node for the DMA channel to use for
159      playback of audio.  This is typically dictated by SOC
160      design. Only used on Power Architecture.
161
162  fsl,capture-dma:
163    $ref: /schemas/types.yaml#/definitions/phandle
164    description: Phandle to a node for the DMA channel to use for
165      capture (recording) of audio.  This is typically dictated
166      by SOC design. Only used on Power Architecture.
167
168required:
169  - compatible
170  - reg
171  - interrupts
172  - fsl,fifo-depth
173
174allOf:
175  - $ref: dai-common.yaml#
176
177unevaluatedProperties: false
178
179examples:
180  - |
181    #include <dt-bindings/interrupt-controller/arm-gic.h>
182    #include <dt-bindings/clock/imx6qdl-clock.h>
183    ssi@2028000 {
184        compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi";
185        reg = <0x02028000 0x4000>;
186        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
187        clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
188                 <&clks IMX6QDL_CLK_SSI1>;
189        clock-names = "ipg", "baud";
190        dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
191        dma-names = "rx", "tx";
192        #sound-dai-cells = <0>;
193        fsl,fifo-depth = <15>;
194    };