fsl,spdif.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/sound/fsl,spdif.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
  8
  9maintainers:
 10  - Shengjiu Wang <shengjiu.wang@nxp.com>
 11
 12description: |
 13  The Freescale S/PDIF audio block is a stereo transceiver that allows the
 14  processor to receive and transmit digital audio via an coaxial cable or
 15  a fibre cable.
 16
 17properties:
 18  compatible:
 19    oneOf:
 20      - items:
 21          - enum:
 22              - fsl,imx35-spdif
 23              - fsl,imx6sx-spdif
 24              - fsl,imx8mm-spdif
 25              - fsl,imx8mn-spdif
 26              - fsl,imx8mq-spdif
 27              - fsl,imx8qm-spdif
 28              - fsl,imx8qxp-spdif
 29              - fsl,imx8ulp-spdif
 30              - fsl,vf610-spdif
 31      - items:
 32          - enum:
 33              - fsl,imx6sl-spdif
 34              - fsl,imx6sx-spdif
 35          - const: fsl,imx35-spdif
 36
 37  reg:
 38    maxItems: 1
 39
 40  interrupts:
 41    minItems: 1
 42    items:
 43      - description: Combined or receive interrupt
 44      - description: Transmit interrupt
 45
 46  dmas:
 47    items:
 48      - description: DMA controller phandle and request line for RX
 49      - description: DMA controller phandle and request line for TX
 50
 51  dma-names:
 52    items:
 53      - const: rx
 54      - const: tx
 55
 56  clocks:
 57    items:
 58      - description: The core clock of spdif controller.
 59      - description: Clock for tx0 and rx0.
 60      - description: Clock for tx1 and rx1.
 61      - description: Clock for tx2 and rx2.
 62      - description: Clock for tx3 and rx3.
 63      - description: Clock for tx4 and rx4.
 64      - description: Clock for tx5 and rx5.
 65      - description: Clock for tx6 and rx6.
 66      - description: Clock for tx7 and rx7.
 67      - description: The spba clock is required when SPDIF is placed as a bus
 68          slave of the Shared Peripheral Bus and when two or more bus masters
 69          (CPU, DMA or DSP) try to access it. This property is optional depending
 70          on the SoC design.
 71      - description: PLL clock source for 8kHz series rate, optional.
 72      - description: PLL clock source for 11khz series rate, optional.
 73    minItems: 9
 74
 75  clock-names:
 76    items:
 77      - const: core
 78      - const: rxtx0
 79      - const: rxtx1
 80      - const: rxtx2
 81      - const: rxtx3
 82      - const: rxtx4
 83      - const: rxtx5
 84      - const: rxtx6
 85      - const: rxtx7
 86      - const: spba
 87      - const: pll8k
 88      - const: pll11k
 89    minItems: 9
 90
 91  big-endian:
 92    $ref: /schemas/types.yaml#/definitions/flag
 93    description: |
 94      If this property is absent, the native endian mode will be in use
 95      as default, or the big endian mode will be in use for all the device
 96      registers. Set this flag for HCDs with big endian descriptors and big
 97      endian registers.
 98
 99  power-domains:
100    maxItems: 1
101
102required:
103  - compatible
104  - reg
105  - interrupts
106  - dmas
107  - dma-names
108  - clocks
109  - clock-names
110
111additionalProperties: false
112
113allOf:
114  - if:
115      properties:
116        compatible:
117          enum:
118            - fsl,imx8qm-spdif
119            - fsl,imx8qxp-spdif
120    then:
121      properties:
122        interrupts:
123          minItems: 2
124    else:
125      properties:
126        interrupts:
127          maxItems: 1
128
129  - if:
130      properties:
131        compatible:
132          contains:
133            enum:
134              - fsl,imx8qm-spdif
135              - fsl,imx8qxp-spdif
136    then:
137      required:
138        - power-domains
139
140examples:
141  - |
142    spdif@2004000 {
143        compatible = "fsl,imx35-spdif";
144        reg = <0x02004000 0x4000>;
145        interrupts = <0 52 0x04>;
146        dmas = <&sdma 14 18 0>,
147               <&sdma 15 18 0>;
148        dma-names = "rx", "tx";
149        clocks = <&clks 197>, <&clks 3>,
150                 <&clks 197>, <&clks 107>,
151                 <&clks 0>, <&clks 118>,
152                 <&clks 62>, <&clks 139>,
153                 <&clks 0>;
154        clock-names = "core", "rxtx0",
155                      "rxtx1", "rxtx2",
156                      "rxtx3", "rxtx4",
157                      "rxtx5", "rxtx6",
158                      "rxtx7";
159        big-endian;
160    };