fsl,esai.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/sound/fsl,esai.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Freescale Enhanced Serial Audio Interface (ESAI) Controller
  8
  9maintainers:
 10  - Shengjiu Wang <shengjiu.wang@nxp.com>
 11  - Frank Li <Frank.Li@nxp.com>
 12
 13description:
 14  The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port
 15  for serial communication with a variety of serial devices, including industry
 16  standard codecs, Sony/Phillips Digital Interface (S/PDIF) transceivers, and
 17  other DSPs. It has up to six transmitters and four receivers.
 18
 19properties:
 20  compatible:
 21    oneOf:
 22      - enum:
 23          - fsl,imx35-esai
 24          - fsl,imx6ull-esai
 25          - fsl,vf610-esai
 26      - items:
 27          - enum:
 28              - fsl,imx8qm-esai
 29          - const: fsl,imx6ull-esai
 30
 31  reg:
 32    maxItems: 1
 33
 34  interrupts:
 35    maxItems: 1
 36
 37  clocks:
 38    minItems: 3
 39    items:
 40      - description:
 41          The core clock used to access registers.
 42      - description:
 43          The esai baud clock for esai controller used to
 44          derive HCK, SCK and FS.
 45      - description:
 46          The system clock derived from ahb clock used to
 47          derive HCK, SCK and FS.
 48      - description:
 49          The spba clock is required when ESAI is placed as a
 50          bus slave of the Shared Peripheral Bus and when two
 51          or more bus masters (CPU, DMA or DSP) try to access
 52          it. This property is optional depending on the SoC
 53          design.
 54
 55  clock-names:
 56    minItems: 3
 57    items:
 58      - const: core
 59      - const: extal
 60      - const: fsys
 61      - const: spba
 62
 63  dmas:
 64    minItems: 2
 65    maxItems: 2
 66
 67  dma-names:
 68    items:
 69      - const: rx
 70      - const: tx
 71
 72  power-domains:
 73    maxItems: 1
 74
 75  fsl,fifo-depth:
 76    $ref: /schemas/types.yaml#/definitions/uint32
 77    default: 64
 78    description:
 79      The number of elements in the transmit and receive
 80      FIFOs. This number is the maximum allowed value for
 81      TFCR[TFWM] or RFCR[RFWM].
 82
 83  fsl,esai-synchronous:
 84    $ref: /schemas/types.yaml#/definitions/flag
 85    description:
 86      This is a boolean property. If present, indicating
 87      that ESAI would work in the synchronous mode, which
 88      means all the settings for Receiving would be
 89      duplicated from Transmission related registers.
 90
 91  big-endian:
 92    $ref: /schemas/types.yaml#/definitions/flag
 93    description:
 94      If this property is absent, the native endian mode
 95      will be in use as default, or the big endian mode
 96      will be in use for all the device registers.
 97
 98required:
 99  - compatible
100  - reg
101  - interrupts
102  - clocks
103  - clock-names
104  - dmas
105  - dma-names
106
107unevaluatedProperties: false
108
109allOf:
110  - $ref: dai-common.yaml#
111  - if:
112      properties:
113        compatible:
114          contains:
115            const: fsl,imx8qm-esai
116    then:
117      required:
118        - power-domains
119    else:
120      properties:
121        power-domains: false
122
123examples:
124  - |
125    esai@2024000 {
126      compatible = "fsl,imx35-esai";
127      reg = <0x02024000 0x4000>;
128      interrupts = <0 51 0x04>;
129      clocks = <&clks 208>, <&clks 118>, <&clks 208>;
130      clock-names = "core", "extal", "fsys";
131      dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
132      dma-names = "rx", "tx";
133      fsl,fifo-depth = <128>;
134      fsl,esai-synchronous;
135      big-endian;
136    };