dlg,da7213.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/sound/dlg,da7213.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Dialog Semiconductor DA7212/DA7213 Audio Codec
  8
  9maintainers:
 10  - Support Opensource <support.opensource@diasemi.com>
 11
 12allOf:
 13  - $ref: dai-common.yaml#
 14
 15properties:
 16  compatible:
 17    enum:
 18      - dlg,da7212
 19      - dlg,da7213
 20
 21  reg:
 22    maxItems: 1
 23
 24  clocks:
 25    maxItems: 1
 26
 27  clock-names:
 28    const: mclk
 29
 30  "#sound-dai-cells":
 31    const: 0
 32
 33  dlg,micbias1-lvl:
 34    description: Voltage (mV) for Mic Bias 1
 35    $ref: /schemas/types.yaml#/definitions/uint32
 36    enum: [ 1600, 2200, 2500, 3000 ]
 37
 38  dlg,micbias2-lvl:
 39    description: Voltage (mV) for Mic Bias 2
 40    $ref: /schemas/types.yaml#/definitions/uint32
 41    enum: [ 1600, 2200, 2500, 3000 ]
 42
 43  dlg,dmic-data-sel:
 44    description: DMIC channel select based on clock edge
 45    enum: [ lrise_rfall, lfall_rrise ]
 46
 47  dlg,dmic-samplephase:
 48    description: When to sample audio from DMIC
 49    enum: [ on_clkedge, between_clkedge ]
 50
 51  dlg,dmic-clkrate:
 52    description: DMIC clock frequency (Hz)
 53    $ref: /schemas/types.yaml#/definitions/uint32
 54    enum: [ 1500000, 3000000 ]
 55
 56  VDDA-supply:
 57    description: Analogue power supply
 58
 59  VDDIO-supply:
 60    description: I/O power supply
 61
 62  VDDMIC-supply:
 63    description: Mic Bias
 64
 65  VDDSP-supply:
 66    description: Speaker supply
 67
 68  ports:
 69    $ref: audio-graph-port.yaml#/definitions/ports
 70
 71  port:
 72    $ref: audio-graph-port.yaml#
 73    unevaluatedProperties: false
 74
 75required:
 76  - compatible
 77  - reg
 78
 79unevaluatedProperties: false
 80
 81examples:
 82  - |
 83    i2c {
 84        #address-cells = <1>;
 85        #size-cells = <0>;
 86
 87        codec@1a {
 88            compatible = "dlg,da7213";
 89            reg = <0x1a>;
 90
 91            clocks = <&clks 201>;
 92            clock-names = "mclk";
 93
 94            #sound-dai-cells = <0>;
 95
 96            dlg,micbias1-lvl = <2500>;
 97            dlg,micbias2-lvl = <2500>;
 98
 99            dlg,dmic-data-sel = "lrise_rfall";
100            dlg,dmic-samplephase = "between_clkedge";
101            dlg,dmic-clkrate = <3000000>;
102        };
103    };