keystone-navigator-qmss.txt

  1* Texas Instruments Keystone Navigator Queue Management SubSystem driver
  2
  3The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of
  4the main hardware sub system which forms the backbone of the Keystone
  5multi-core Navigator. QMSS consist of queue managers, packed-data structure
  6processors(PDSP), linking RAM, descriptor pools and infrastructure
  7Packet DMA.
  8The Queue Manager is a hardware module that is responsible for accelerating
  9management of the packet queues. Packets are queued/de-queued by writing or
 10reading descriptor address to a particular memory mapped location. The PDSPs
 11perform QMSS related functions like accumulation, QoS, or event management.
 12Linking RAM registers are used to link the descriptors which are stored in
 13descriptor RAM. Descriptor RAM is configurable as internal or external memory.
 14The QMSS driver manages the PDSP setups, linking RAM regions,
 15queue pool management (allocation, push, pop and notify) and descriptor
 16pool management.
 17
 18
 19Required properties:
 20- compatible	: Must be "ti,keystone-navigator-qmss".
 21		: Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
 22- clocks	: phandle to the reference clock for this device.
 23- queue-range	: <start number> total range of queue numbers for the device.
 24- linkram0	: <address size> for internal link ram, where size is the total
 25		  link ram entries.
 26- linkram1	: <address size> for external link ram, where size is the total
 27		  external link ram entries. If the address is specified as "0"
 28		  driver will allocate memory.
 29- qmgrs         : child node describing the individual queue managers on the
 30		  SoC. On keystone 1 devices there should be only one node.
 31		  On keystone 2 devices there can be more than 1 node.
 32  -- managed-queues	: the actual queues managed by each queue manager
 33			  instance, specified as <"base queue #" "# of queues">.
 34  -- reg		: Address and size of the register set for the device.
 35			  Register regions should be specified in the following
 36			  order
 37			  - Queue Peek region.
 38			  - Queue status RAM.
 39			  - Queue configuration region.
 40			  - Descriptor memory setup region.
 41			  - Queue Management/Queue Proxy region for queue Push.
 42			  - Queue Management/Queue Proxy region for queue Pop.
 43
 44For QMSS on K2G SoC, following QM reg indexes are used in that order
 45			  - Queue Peek region.
 46			  - Queue configuration region.
 47			  - Queue Management/Queue Proxy region for queue Push/Pop.
 48
 49- queue-pools	: child node classifying the queue ranges into pools.
 50		  Queue ranges are grouped into 3 type of pools:
 51		  - qpend	    : pool of qpend(interruptible) queues
 52		  - general-purpose : pool of general queues, primarily used
 53				      as free descriptor queues or the
 54				      transmit DMA queues.
 55		  - accumulator	    : pool of queues on PDSP accumulator channel
 56		  Each range can have the following properties:
 57  -- qrange		: number of queues to use per queue range, specified as
 58			  <"base queue #" "# of queues">.
 59  -- interrupts		: Optional property to specify the interrupt mapping
 60			  for interruptible queues. The driver additionally sets
 61			  the interrupt affinity hint based on the cpu mask.
 62  -- qalloc-by-id	: Optional property to specify that the queues in this
 63			  range can only be allocated by queue id.
 64  -- accumulator	: Accumulator channel specification. Any of the PDSPs in
 65			  QMSS can be loaded with the accumulator firmware. The
 66			  accumulator firmware’s job is to poll a select number of
 67			  queues looking for descriptors that have been pushed
 68			  into them. Descriptors are popped from the queue and
 69			  placed in a buffer provided by the host. When the list
 70			  becomes full or a programmed time period expires, the
 71			  accumulator triggers an interrupt to the host to read
 72			  the buffer for descriptor information. This firmware
 73			  comes in 16, 32, and 48 channel builds. Each of these
 74			  channels can be configured to monitor 32 contiguous
 75			  queues.  Accumulator channel property is specified as:
 76			  <pdsp-id, channel, entries, pacing mode, latency>
 77			  pdsp-id     : QMSS PDSP running accumulator firmware
 78					on which the channel has to be
 79					configured
 80			  channel     : Accumulator channel number
 81			  entries     : Size of the accumulator descriptor list
 82			  pacing mode : Interrupt pacing mode
 83					0 : None, i.e interrupt on list full only
 84					1 : Time delay since last interrupt
 85					2 : Time delay since first new packet
 86					3 : Time delay since last new packet
 87			  latency     : time to delay the interrupt, specified
 88					in microseconds.
 89  -- multi-queue	: Optional property to specify that the channel has to
 90			  monitor up to 32 queues starting at the base queue #.
 91- descriptor-regions	: child node describing the memory regions for keystone
 92			  navigator packet DMA descriptors. The memory for
 93			  descriptors will be allocated by the driver.
 94  -- id				: region number in QMSS.
 95  -- region-spec		: specifies the number of descriptors in the
 96				  region, specified as
 97				  <"# of descriptors" "descriptor size">.
 98  -- link-index			: start index, i.e. index of the first
 99				  descriptor in the region.
100
101Optional properties:
102- dma-coherent	: Present if DMA operations are coherent.
103- pdsps		: child node describing the PDSP configuration.
104  -- firmware		: firmware to be loaded on the PDSP.
105  -- id			: the qmss pdsp that will run the firmware.
106  -- reg		: Address and size of the register set for the PDSP.
107			  Register regions should be specified in the following
108			  order
109			  - PDSP internal RAM region.
110			  - PDSP control/status region registers.
111			  - QMSS interrupt distributor registers.
112			  - PDSP command interface region.
113
114Example:
115
116qmss: qmss@2a40000 {
117	compatible = "ti,keystone-qmss";
118	dma-coherent;
119	#address-cells = <1>;
120	#size-cells = <1>;
121	clocks = <&chipclk13>;
122	ranges;
123	queue-range	= <0 0x4000>;
124	linkram0	= <0x100000 0x8000>;
125	linkram1	= <0x0 0x10000>;
126
127	qmgrs {
128		#address-cells = <1>;
129		#size-cells = <1>;
130		ranges;
131		qmgr0 {
132			managed-queues = <0 0x2000>;
133			reg = <0x2a40000 0x20000>,
134			      <0x2a06000 0x400>,
135			      <0x2a02000 0x1000>,
136			      <0x2a03000 0x1000>,
137			      <0x23a80000 0x20000>,
138			      <0x2a80000 0x20000>;
139		};
140
141		qmgr1 {
142			managed-queues = <0x2000 0x2000>;
143			reg = <0x2a60000 0x20000>,
144			      <0x2a06400 0x400>,
145			      <0x2a04000 0x1000>,
146			      <0x2a05000 0x1000>,
147			      <0x23aa0000 0x20000>,
148			      <0x2aa0000 0x20000>;
149		};
150	};
151	queue-pools {
152		qpend {
153			qpend-0 {
154				qrange = <658 8>;
155				interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
156					     0 43 0xf04 0 44 0xf04 0 45 0xf04
157					     0 46 0xf04 0 47 0xf04>;
158			};
159			qpend-1 {
160				qrange = <8704 16>;
161				interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
162					      0 51 0xf04 0 52 0xf04 0 53 0xf04
163					      0 54 0xf04 0 55 0xf04 0 56 0xf04
164					      0 57 0xf04 0 58 0xf04 0 59 0xf04
165					      0 60 0xf04 0 61 0xf04 0 62 0xf04
166					      0 63 0xf04>;
167				qalloc-by-id;
168			};
169			qpend-2 {
170				qrange = <8720 16>;
171				interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
172					      0 59 0xf04 0 68 0xf04 0 69 0xf04
173					      0 70 0xf04 0 71 0xf04 0 72 0xf04
174					      0 73 0xf04 0 74 0xf04 0 75 0xf04
175					      0 76 0xf04 0 77 0xf04 0 78 0xf04
176					      0 79 0xf04>;
177			};
178		};
179		general-purpose {
180			gp-0 {
181				qrange = <4000 64>;
182			};
183			netcp-tx {
184				qrange = <640 9>;
185				qalloc-by-id;
186			};
187		};
188		accumulator {
189			acc-0 {
190				qrange = <128 32>;
191				accumulator = <0 36 16 2 50>;
192				interrupts = <0 215 0xf01>;
193				multi-queue;
194				qalloc-by-id;
195			};
196			acc-1 {
197				qrange = <160 32>;
198				accumulator = <0 37 16 2 50>;
199				interrupts = <0 216 0xf01>;
200				multi-queue;
201			};
202			acc-2 {
203				qrange = <192 32>;
204				accumulator = <0 38 16 2 50>;
205				interrupts = <0 217 0xf01>;
206				multi-queue;
207			};
208			acc-3 {
209				qrange = <224 32>;
210				accumulator = <0 39 16 2 50>;
211				interrupts = <0 218 0xf01>;
212				multi-queue;
213			};
214		};
215	};
216	descriptor-regions {
217		#address-cells = <1>;
218		#size-cells = <1>;
219		ranges;
220		region-12 {
221			id = <12>;
222			region-spec = <8192 128>; /* num_desc desc_size */
223			link-index = <0x4000>;
224		};
225	};
226	pdsps {
227		#address-cells = <1>;
228		#size-cells = <1>;
229		ranges;
230		pdsp0@2a10000 {
231			reg = <0x2a10000 0x1000>,
232			      <0x2a0f000 0x100>,
233			      <0x2a0c000 0x3c8>,
234			      <0x2a20000 0x4000>;
235			id = <0>;
236		};
237	};
238}; /* qmss */