exynos-usi.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Samsung's Exynos USI (Universal Serial Interface)
  8
  9maintainers:
 10  - Sam Protsenko <semen.protsenko@linaro.org>
 11  - Krzysztof Kozlowski <krzk@kernel.org>
 12
 13description: |
 14  The USI IP-core provides configurable support for serial protocols, enabling
 15  different serial communication modes depending on the version.
 16
 17  In USIv1, configurations are available to enable either one or two protocols
 18  simultaneously in select combinations - High-Speed I2C0, High-Speed
 19  I2C1, SPI, UART, High-Speed I2C0 and I2C1 or both High-Speed
 20  I2C1 and UART.
 21
 22  In USIv2, only one protocol can be active at a time, either UART, SPI, or
 23  High-Speed I2C.
 24
 25  The USI core shares internal circuits across protocols, meaning only the
 26  selected configuration is active at any given time. USI is modeled as a node
 27  with zero or more child nodes, each representing a serial sub-node device. The
 28  mode setting selects which particular function will be used.
 29
 30properties:
 31  $nodename:
 32    pattern: "^usi@[0-9a-f]+$"
 33
 34  compatible:
 35    oneOf:
 36      - items:
 37          - enum:
 38              - google,gs101-usi
 39              - samsung,exynos2200-usi
 40              - samsung,exynosautov9-usi
 41              - samsung,exynosautov920-usi
 42          - const: samsung,exynos850-usi
 43      - enum:
 44          - samsung,exynos850-usi
 45          - samsung,exynos8895-usi
 46
 47  reg:
 48    maxItems: 1
 49
 50  clocks:
 51    maxItems: 2
 52
 53  clock-names:
 54    items:
 55      - const: pclk
 56      - const: ipclk
 57
 58  ranges: true
 59
 60  "#address-cells":
 61    const: 1
 62
 63  "#size-cells":
 64    const: 1
 65
 66  samsung,sysreg:
 67    $ref: /schemas/types.yaml#/definitions/phandle-array
 68    items:
 69      - items:
 70          - description: phandle to System Register syscon node
 71          - description: offset of SW_CONF register for this USI controller
 72    description:
 73      Should be phandle/offset pair. The phandle to System Register syscon node
 74      (for the same domain where this USI controller resides) and the offset
 75      of SW_CONF register for this USI controller.
 76
 77  samsung,mode:
 78    $ref: /schemas/types.yaml#/definitions/uint32
 79    enum: [0, 1, 2, 3, 4, 5, 6]
 80    description:
 81      Selects USI function (which serial protocol to use). Refer to
 82      <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
 83
 84  samsung,clkreq-on:
 85    type: boolean
 86    description:
 87      Enable this property if underlying protocol requires the clock to be
 88      continuously provided without automatic gating. As suggested by SoC
 89      manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
 90      multi-master mode. Usually this property is needed if USI mode is set
 91      to "UART".
 92
 93      This property is optional.
 94
 95patternProperties:
 96  "^i2c@[0-9a-f]+$":
 97    $ref: /schemas/i2c/i2c-exynos5.yaml
 98    description: Child node describing underlying I2C
 99
100  "^serial@[0-9a-f]+$":
101    $ref: /schemas/serial/samsung_uart.yaml
102    description: Child node describing underlying UART/serial
103
104  "^spi@[0-9a-f]+$":
105    $ref: /schemas/spi/samsung,spi.yaml
106    description: Child node describing underlying SPI
107
108required:
109  - compatible
110  - ranges
111  - "#address-cells"
112  - "#size-cells"
113  - samsung,sysreg
114  - samsung,mode
115
116allOf:
117  - if:
118      properties:
119        compatible:
120          contains:
121            enum:
122              - samsung,exynos850-usi
123
124    then:
125      properties:
126        reg:
127          maxItems: 1
128
129        clocks:
130          items:
131            - description: Bus (APB) clock
132            - description: Operating clock for UART/SPI/I2C protocol
133
134        clock-names:
135          maxItems: 2
136
137        samsung,mode:
138          enum: [0, 1, 2, 3]
139
140      required:
141        - reg
142        - clocks
143        - clock-names
144
145  - if:
146      properties:
147        compatible:
148          contains:
149            enum:
150              - samsung,exynos8895-usi
151
152    then:
153      properties:
154        reg: false
155
156        clocks:
157          items:
158            - description: Bus (APB) clock
159            - description: Operating clock for UART/SPI protocol
160
161        clock-names:
162          maxItems: 2
163
164        samsung,clkreq-on: false
165
166      required:
167        - clocks
168        - clock-names
169
170additionalProperties: false
171
172examples:
173  - |
174    #include <dt-bindings/interrupt-controller/arm-gic.h>
175    #include <dt-bindings/soc/samsung,exynos-usi.h>
176
177    usi0: usi@138200c0 {
178        compatible = "samsung,exynos850-usi";
179        reg = <0x138200c0 0x20>;
180        samsung,sysreg = <&sysreg_peri 0x1010>;
181        samsung,mode = <USI_MODE_UART>;
182        samsung,clkreq-on; /* needed for UART mode */
183        #address-cells = <1>;
184        #size-cells = <1>;
185        ranges;
186        clocks = <&cmu_peri 32>, <&cmu_peri 31>;
187        clock-names = "pclk", "ipclk";
188
189        serial_0: serial@13820000 {
190            compatible = "samsung,exynos850-uart";
191            reg = <0x13820000 0xc0>;
192            interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
193            clocks = <&cmu_peri 32>, <&cmu_peri 31>;
194            clock-names = "uart", "clk_uart_baud0";
195        };
196
197        hsi2c_0: i2c@13820000 {
198            compatible = "samsung,exynos850-hsi2c", "samsung,exynosautov9-hsi2c";
199            reg = <0x13820000 0xc0>;
200            interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
201            #address-cells = <1>;
202            #size-cells = <0>;
203            clocks = <&cmu_peri 31>, <&cmu_peri 32>;
204            clock-names = "hsi2c", "hsi2c_pclk";
205            status = "disabled";
206        };
207    };