qcom,smsm.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/soc/qcom/qcom,smsm.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm Shared Memory State Machine
  8
  9maintainers:
 10  - Andy Gross <agross@kernel.org>
 11  - Bjorn Andersson <bjorn.andersson@linaro.org>
 12  - Krzysztof Kozlowski <krzk@kernel.org>
 13
 14description:
 15  The Shared Memory State Machine facilitates broadcasting of single bit state
 16  information between the processors in a Qualcomm SoC. Each processor is
 17  assigned 32 bits of state that can be modified. A processor can through a
 18  matrix of bitmaps signal subscription of notifications upon changes to a
 19  certain bit owned by a certain remote processor.
 20
 21properties:
 22  compatible:
 23    const: qcom,smsm
 24
 25  '#address-cells':
 26    const: 1
 27
 28  qcom,local-host:
 29    $ref: /schemas/types.yaml#/definitions/uint32
 30    default: 0
 31    description:
 32      Identifier of the local processor in the list of hosts, or in other words
 33      specifier of the column in the subscription matrix representing the local
 34      processor.
 35
 36  mboxes:
 37    minItems: 1
 38    maxItems: 5
 39    description:
 40      Reference to the mailbox representing the outgoing doorbell in APCS for
 41      this client. Each entry represents the N:th remote processor by index
 42      (0-indexed).
 43
 44  '#size-cells':
 45    const: 0
 46
 47patternProperties:
 48  "^qcom,ipc-[1-4]$":
 49    $ref: /schemas/types.yaml#/definitions/phandle-array
 50    items:
 51      - items:
 52          - description: phandle to a syscon node representing the APCS registers
 53          - description: u32 representing offset to the register within the syscon
 54          - description: u32 representing the ipc bit within the register
 55    description:
 56      Three entries specifying the outgoing ipc bit used for signaling the N:th
 57      remote processor.
 58    deprecated: true
 59
 60  "@[0-9a-f]$":
 61    type: object
 62    description:
 63      Each processor's state bits are described by a subnode of the SMSM device
 64      node.  Nodes can either be flagged as an interrupt-controller to denote a
 65      remote processor's state bits or the local processors bits.  The node
 66      names are not important.
 67
 68    properties:
 69      reg:
 70        maxItems: 1
 71
 72      interrupt-controller:
 73        description:
 74          Marks the entry as a interrupt-controller and the state bits to
 75          belong to a remote processor.
 76
 77      '#interrupt-cells':
 78        const: 2
 79
 80      interrupts:
 81        maxItems: 1
 82        description:
 83          One entry specifying remote IRQ used by the remote processor to
 84          signal changes of its state bits.
 85
 86      '#qcom,smem-state-cells':
 87        $ref: /schemas/types.yaml#/definitions/uint32
 88        const: 1
 89        description:
 90          Required for local entry. Denotes bit number.
 91
 92    required:
 93      - reg
 94
 95    oneOf:
 96      - required:
 97          - '#qcom,smem-state-cells'
 98      - required:
 99          - interrupt-controller
100          - '#interrupt-cells'
101          - interrupts
102
103    additionalProperties: false
104
105required:
106  - compatible
107  - '#address-cells'
108  - '#size-cells'
109
110oneOf:
111  - required:
112      - mboxes
113  - anyOf:
114      - required:
115          - qcom,ipc-1
116      - required:
117          - qcom,ipc-2
118      - required:
119          - qcom,ipc-3
120      - required:
121          - qcom,ipc-4
122
123additionalProperties: false
124
125examples:
126  # The following example shows the SMEM setup for controlling properties of
127  # the wireless processor, defined from the 8974 apps processor's
128  # point-of-view. It encompasses one outbound entry and the outgoing interrupt
129  # for the wireless processor.
130  - |
131    #include <dt-bindings/interrupt-controller/arm-gic.h>
132
133    shared-memory {
134        compatible = "qcom,smsm";
135        #address-cells = <1>;
136        #size-cells = <0>;
137        mboxes = <0>, <0>, <0>, <&apcs 19>;
138
139        apps_smsm: apps@0 {
140            reg = <0>;
141            #qcom,smem-state-cells = <1>;
142        };
143
144        wcnss_smsm: wcnss@7 {
145            reg = <7>;
146            interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
147            interrupt-controller;
148            #interrupt-cells = <2>;
149        };
150    };