qcom,msm-uartdm.yaml

  1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/serial/qcom,msm-uartdm.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm MSM Serial UARTDM
  8
  9maintainers:
 10  - Andy Gross <agross@kernel.org>
 11  - Bjorn Andersson <bjorn.andersson@linaro.org>
 12  - Krzysztof Kozlowski <krzk@kernel.org>
 13
 14description: |
 15  The MSM serial UARTDM hardware is designed for high-speed use cases where the
 16  transmit and/or receive channels can be offloaded to a dma-engine. From a
 17  software perspective it's mostly compatible with the MSM serial UART except
 18  that it supports reading and writing multiple characters at a time.
 19
 20  Note:: Aliases may be defined to ensure the correct ordering of the UARTs.
 21  The alias serialN will result in the UART being assigned port N.  If any
 22  serialN alias exists, then an alias must exist for each enabled UART.  The
 23  serialN aliases should be in a .dts file instead of in a .dtsi file.
 24
 25properties:
 26  compatible:
 27    items:
 28      - enum:
 29          - qcom,msm-uartdm-v1.1
 30          - qcom,msm-uartdm-v1.2
 31          - qcom,msm-uartdm-v1.3
 32          - qcom,msm-uartdm-v1.4
 33      - const: qcom,msm-uartdm
 34
 35  clocks:
 36    maxItems: 2
 37
 38  clock-names:
 39    items:
 40      - const: core
 41      - const: iface
 42
 43  dmas:
 44    maxItems: 2
 45
 46  dma-names:
 47    items:
 48      - const: tx
 49      - const: rx
 50
 51  interconnects:
 52    maxItems: 1
 53
 54  interrupts:
 55    maxItems: 1
 56
 57  operating-points-v2: true
 58
 59  power-domains:
 60    maxItems: 1
 61
 62  qcom,rx-crci:
 63    $ref: /schemas/types.yaml#/definitions/uint32
 64    description:
 65      Identificator for Client Rate Control Interface to be used with RX DMA
 66      channel. Required when using DMA for reception with UARTDM v1.3 and
 67      below.
 68
 69  qcom,tx-crci:
 70    $ref: /schemas/types.yaml#/definitions/uint32
 71    description:
 72      Identificator for Client Rate Control Interface to be used with TX DMA
 73      channel. Required when using DMA for transmission with UARTDM v1.3 and
 74      below.
 75
 76  reg:
 77    minItems: 1
 78    items:
 79      - description: Main control registers
 80      - description: An optional second register location shall specify the GSBI control region.
 81
 82required:
 83  - compatible
 84  - clock-names
 85  - clocks
 86  - interrupts
 87  - reg
 88
 89allOf:
 90  - $ref: /schemas/serial/serial.yaml#
 91
 92  - if:
 93      properties:
 94        compatible:
 95          contains:
 96            const: qcom,msm-uartdm-v1.3
 97    then:
 98      properties:
 99        reg:
100          minItems: 2
101    else:
102      properties:
103        reg:
104          maxItems: 1
105
106unevaluatedProperties: false
107
108examples:
109  - |
110    #include <dt-bindings/interconnect/qcom,msm8996.h>
111    #include <dt-bindings/interrupt-controller/arm-gic.h>
112    #include <dt-bindings/power/qcom-rpmpd.h>
113
114    serial@f991e000 {
115        compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
116        reg = <0xf991e000 0x1000>;
117        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
118        clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>;
119        clock-names = "core", "iface";
120        dmas = <&dma0 0>, <&dma0 1>;
121        dma-names = "tx", "rx";
122        power-domains = <&rpmpd MSM8996_VDDCX>;
123        operating-points-v2 = <&uart_opp_table>;
124        interconnects = <&pnoc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
125    };