cpus.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/riscv/cpus.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: RISC-V CPUs
  8
  9maintainers:
 10  - Paul Walmsley <paul.walmsley@sifive.com>
 11  - Palmer Dabbelt <palmer@sifive.com>
 12  - Conor Dooley <conor@kernel.org>
 13
 14description: |
 15  This document uses some terminology common to the RISC-V community
 16  that is not widely used, the definitions of which are listed here:
 17
 18  hart: A hardware execution context, which contains all the state
 19  mandated by the RISC-V ISA: a PC and some registers.  This
 20  terminology is designed to disambiguate software's view of execution
 21  contexts from any particular microarchitectural implementation
 22  strategy.  For example, an Intel laptop containing one socket with
 23  two cores, each of which has two hyperthreads, could be described as
 24  having four harts.
 25
 26allOf:
 27  - $ref: /schemas/cpu.yaml#
 28  - $ref: extensions.yaml
 29  - if:
 30      not:
 31        properties:
 32          compatible:
 33            contains:
 34              enum:
 35                - thead,c906
 36                - thead,c910
 37                - thead,c920
 38    then:
 39      properties:
 40        thead,vlenb: false
 41
 42properties:
 43  compatible:
 44    oneOf:
 45      - items:
 46          - enum:
 47              - amd,mbv32
 48              - amd,mbv64
 49              - andestech,ax45mp
 50              - canaan,k210
 51              - nuclei,ux900
 52              - sifive,bullet0
 53              - sifive,e5
 54              - sifive,e7
 55              - sifive,e71
 56              - sifive,p550
 57              - sifive,rocket0
 58              - sifive,s7
 59              - sifive,u5
 60              - sifive,u54
 61              - sifive,u7
 62              - sifive,u74
 63              - sifive,u74-mc
 64              - spacemit,x60
 65              - thead,c906
 66              - thead,c908
 67              - thead,c910
 68              - thead,c920
 69          - const: riscv
 70      - items:
 71          - enum:
 72              - sifive,e51
 73              - sifive,u54-mc
 74              - sifive,x280
 75          - const: sifive,rocket0
 76          - const: riscv
 77      - const: riscv    # Simulator only
 78    description:
 79      Identifies that the hart uses the RISC-V instruction set
 80      and identifies the type of the hart.
 81
 82  mmu-type:
 83    description:
 84      Identifies the largest MMU address translation mode supported by
 85      this hart.  These values originate from the RISC-V Privileged
 86      Specification document, available from
 87      https://riscv.org/specifications/
 88    $ref: /schemas/types.yaml#/definitions/string
 89    enum:
 90      - riscv,sv32
 91      - riscv,sv39
 92      - riscv,sv48
 93      - riscv,sv57
 94      - riscv,none
 95
 96  reg:
 97    description:
 98      The hart ID of this CPU node.
 99
100  riscv,cbom-block-size:
101    $ref: /schemas/types.yaml#/definitions/uint32
102    description:
103      The blocksize in bytes for the Zicbom cache operations.
104
105  riscv,cbop-block-size:
106    $ref: /schemas/types.yaml#/definitions/uint32
107    description:
108      The blocksize in bytes for the Zicbop cache operations.
109
110  riscv,cboz-block-size:
111    $ref: /schemas/types.yaml#/definitions/uint32
112    description:
113      The blocksize in bytes for the Zicboz cache operations.
114
115  thead,vlenb:
116    $ref: /schemas/types.yaml#/definitions/uint32
117    description:
118      VLEN/8, the vector register length in bytes. This property is required on
119      thead systems where the vector register length is not identical on all harts, or
120      the vlenb CSR is not available.
121
122  # RISC-V has multiple properties for cache op block sizes as the sizes
123  # differ between individual CBO extensions
124  cache-op-block-size: false
125  # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
126  timebase-frequency: false
127
128  interrupt-controller:
129    type: object
130    $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml#
131
132  cpu-idle-states:
133    $ref: /schemas/types.yaml#/definitions/phandle-array
134    items:
135      maxItems: 1
136    description: |
137      List of phandles to idle state nodes supported
138      by this hart (see ./idle-states.yaml).
139
140  capacity-dmips-mhz:
141    description:
142      u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
143      DMIPS/MHz, relative to highest capacity-dmips-mhz
144      in the system.
145
146anyOf:
147  - required:
148      - riscv,isa
149  - required:
150      - riscv,isa-base
151
152dependencies:
153  riscv,isa-base: [ "riscv,isa-extensions" ]
154  riscv,isa-extensions: [ "riscv,isa-base" ]
155
156required:
157  - interrupt-controller
158
159unevaluatedProperties: false
160
161examples:
162  - |
163    // Example 1: SiFive Freedom U540G Development Kit
164    cpus {
165        #address-cells = <1>;
166        #size-cells = <0>;
167        timebase-frequency = <1000000>;
168        cpu@0 {
169                clock-frequency = <0>;
170                compatible = "sifive,rocket0", "riscv";
171                device_type = "cpu";
172                i-cache-block-size = <64>;
173                i-cache-sets = <128>;
174                i-cache-size = <16384>;
175                reg = <0>;
176                riscv,isa-base = "rv64i";
177                riscv,isa-extensions = "i", "m", "a", "c";
178
179                cpu_intc0: interrupt-controller {
180                        #interrupt-cells = <1>;
181                        compatible = "riscv,cpu-intc";
182                        interrupt-controller;
183                };
184        };
185        cpu@1 {
186                clock-frequency = <0>;
187                compatible = "sifive,rocket0", "riscv";
188                d-cache-block-size = <64>;
189                d-cache-sets = <64>;
190                d-cache-size = <32768>;
191                d-tlb-sets = <1>;
192                d-tlb-size = <32>;
193                device_type = "cpu";
194                i-cache-block-size = <64>;
195                i-cache-sets = <64>;
196                i-cache-size = <32768>;
197                i-tlb-sets = <1>;
198                i-tlb-size = <32>;
199                mmu-type = "riscv,sv39";
200                reg = <1>;
201                tlb-split;
202                riscv,isa-base = "rv64i";
203                riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
204
205                cpu_intc1: interrupt-controller {
206                        #interrupt-cells = <1>;
207                        compatible = "riscv,cpu-intc";
208                        interrupt-controller;
209                };
210        };
211    };
212
213  - |
214    // Example 2: Spike ISA Simulator with 1 Hart
215    cpus {
216        #address-cells = <1>;
217        #size-cells = <0>;
218        cpu@0 {
219                device_type = "cpu";
220                reg = <0>;
221                compatible = "riscv";
222                mmu-type = "riscv,sv48";
223                riscv,isa-base = "rv64i";
224                riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
225
226                interrupt-controller {
227                        #interrupt-cells = <1>;
228                        interrupt-controller;
229                        compatible = "riscv,cpu-intc";
230                };
231        };
232    };
233...