renesas,rzv2h-usb2phy-reset.yaml

 1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 2%YAML 1.2
 3---
 4$id: http://devicetree.org/schemas/reset/renesas,rzv2h-usb2phy-reset.yaml#
 5$schema: http://devicetree.org/meta-schemas/core.yaml#
 6
 7title: Renesas RZ/V2H(P) USB2PHY Port reset Control
 8
 9maintainers:
10  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11
12description:
13  The RZ/V2H(P) USB2PHY Control mainly controls Port reset and power down of the
14  USB2.0 PHY.
15
16properties:
17  compatible:
18    oneOf:
19      - items:
20          - const: renesas,r9a09g056-usb2phy-reset # RZ/V2N
21          - const: renesas,r9a09g057-usb2phy-reset
22
23      - const: renesas,r9a09g057-usb2phy-reset # RZ/V2H(P)
24
25  reg:
26    maxItems: 1
27
28  clocks:
29    maxItems: 1
30
31  resets:
32    maxItems: 1
33
34  power-domains:
35    maxItems: 1
36
37  '#reset-cells':
38    const: 0
39
40required:
41  - compatible
42  - reg
43  - clocks
44  - resets
45  - power-domains
46  - '#reset-cells'
47
48additionalProperties: false
49
50examples:
51  - |
52    #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
53
54    reset-controller@15830000 {
55        compatible = "renesas,r9a09g057-usb2phy-reset";
56        reg = <0x15830000 0x10000>;
57        clocks = <&cpg CPG_MOD 0xb6>;
58        resets = <&cpg 0xaf>;
59        power-domains = <&cpg>;
60        #reset-cells = <0>;
61    };