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ti,k3-r5f-rproc.yaml
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linux-6.19.14/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: TI K3 R5F processor subsystems 8 9maintainers: 10 - Suman Anna <s-anna@ti.com> 11 12description: | 13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F 14 processor subsystems/clusters (R5FSS). The dual core cluster can be used 15 either in a LockStep mode providing safety/fault tolerance features or in a 16 Split mode providing two individual compute cores for doubling the compute 17 capacity on most SoCs. These are used together with other processors present 18 on the SoC to achieve various system level goals. 19 20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode 21 called "Single-CPU" mode, where only Core0 is used, but with ability to use 22 Core1's TCMs as well. 23 24 AM62 SoC family support a single R5F core only which runs Device Manager 25 firmware and can also be used as a remote processor with IPC communication. 26 27 Each Dual-Core R5F sub-system is represented as a single DTS node 28 representing the cluster, with a pair of child DT nodes representing 29 the individual R5F cores. Each node has a number of required or optional 30 properties that enable the OS running on the host processor to perform 31 the device management of the remote processor and to communicate with the 32 remote processor. 33 34properties: 35 $nodename: 36 pattern: "^r5fss(@.*)?" 37 38 compatible: 39 enum: 40 - ti,am62-r5fss 41 - ti,am64-r5fss 42 - ti,am654-r5fss 43 - ti,j7200-r5fss 44 - ti,j721e-r5fss 45 - ti,j721s2-r5fss 46 47 power-domains: 48 description: | 49 Should contain a phandle to a PM domain provider node and an args 50 specifier containing the R5FSS device id value. 51 maxItems: 1 52 53 "#address-cells": 54 const: 1 55 56 "#size-cells": 57 const: 1 58 59 ranges: 60 description: | 61 Standard ranges definition providing address translations for 62 local R5F TCM address spaces to bus addresses. 63 64# Optional properties: 65# -------------------- 66 67 ti,cluster-mode: 68 $ref: /schemas/types.yaml#/definitions/uint32 69 description: | 70 Configuration Mode for the Dual R5F cores within the R5F cluster. 71 For most SoCs (AM65x, J721E, J7200, J721s2), 72 It should be either a value of 1 (LockStep mode) or 0 (Split mode) on 73 most SoCs (AM65x, J721E, J7200, J721s2), default is LockStep mode if 74 omitted. 75 For AM64x SoCs, 76 It should be either a value of 0 (Split mode) or 2 (Single-CPU mode) and 77 default is Split mode if omitted. 78 For AM62x SoCs, 79 It should be set as 3 (Single-Core mode) which is also the default if 80 omitted. 81 82# R5F Processor Child Nodes: 83# ========================== 84 85patternProperties: 86 "^r5f@[a-f0-9]+$": 87 type: object 88 description: | 89 The R5F Sub-System device node should define two R5F child nodes, each 90 node representing a TI instantiation of the Arm Cortex R5F core. There 91 are some specific integration differences for the IP like the usage of 92 a Region Address Translator (RAT) for translating the larger SoC bus 93 addresses into a 32-bit address space for the processor. For AM62x, 94 the R5F Sub-System device node should only define one R5F child node 95 as it has only one core available. 96 97 Each R5F core has an associated 64 KB of Tightly-Coupled Memory (TCM) 98 internal memories split between two banks - TCMA and TCMB (further 99 interleaved into two banks TCMB0 and TCMB1). These memories (also called 100 ATCM and BTCM) provide read/write performance on par with the core's L1 101 caches. Each of the TCMs can be enabled or disabled independently and 102 either of them can be configured to appear at that R5F's address 0x0. 103 104 The cores do not use an MMU, but has a Region Address Translator 105 (RAT) module that is accessible only from the R5Fs for providing 106 translations between 32-bit CPU addresses into larger system bus 107 addresses. Cache and memory access settings are provided through a 108 Memory Protection Unit (MPU), programmable only from the R5Fs. 109 110 $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# 111 112 properties: 113 compatible: 114 enum: 115 - ti,am62-r5f 116 - ti,am64-r5f 117 - ti,am654-r5f 118 - ti,j7200-r5f 119 - ti,j721e-r5f 120 - ti,j721s2-r5f 121 122 reg: 123 items: 124 - description: Address and Size of the ATCM internal memory region 125 - description: Address and Size of the BTCM internal memory region 126 127 reg-names: 128 items: 129 - const: atcm 130 - const: btcm 131 132 resets: 133 description: | 134 Should contain the phandle to the reset controller node managing the 135 local resets for this device, and a reset specifier. 136 maxItems: 1 137 138 firmware-name: 139 description: | 140 Should contain the name of the default firmware image 141 file located on the firmware search path 142 143# The following properties are mandatory for R5F Core0 in both LockStep and Split 144# modes, and are mandatory for R5F Core1 _only_ in Split mode. They are unused for 145# R5F Core1 in LockStep mode: 146 147 mboxes: 148 description: | 149 OMAP Mailbox specifier denoting the sub-mailbox, to be used for 150 communication with the remote processor. This property should match 151 with the sub-mailbox node used in the firmware image. 152 maxItems: 1 153 154 memory-region: 155 description: | 156 phandle to the reserved memory nodes to be associated with the 157 remoteproc device. There should be at least two reserved memory nodes 158 defined. The reserved memory nodes should be carveout nodes, and 159 should be defined with a "no-map" property as per the bindings in 160 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt 161 minItems: 2 162 maxItems: 8 163 items: 164 - description: region used for dynamic DMA allocations like vrings and 165 vring buffers 166 - description: region reserved for firmware image sections 167 additionalItems: true 168 169# Optional properties: 170# -------------------- 171# The following properties are optional properties for each of the R5F cores: 172 173 ti,atcm-enable: 174 $ref: /schemas/types.yaml#/definitions/uint32 175 enum: [0, 1] 176 description: | 177 R5F core configuration mode dictating if ATCM should be enabled. The 178 R5F address of ATCM is dictated by ti,loczrama property. Should be 179 either a value of 1 (enabled) or 0 (disabled), default is disabled 180 if omitted. Recommended to enable it for maximizing TCMs. 181 182 ti,btcm-enable: 183 $ref: /schemas/types.yaml#/definitions/uint32 184 enum: [0, 1] 185 description: | 186 R5F core configuration mode dictating if BTCM should be enabled. The 187 R5F address of BTCM is dictated by ti,loczrama property. Should be 188 either a value of 1 (enabled) or 0 (disabled), default is enabled if 189 omitted. 190 191 ti,loczrama: 192 $ref: /schemas/types.yaml#/definitions/uint32 193 enum: [0, 1] 194 description: | 195 R5F core configuration mode dictating which TCM should appear at 196 address 0 (from core's view). Should be either a value of 1 (ATCM 197 at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted. 198 199 sram: 200 $ref: /schemas/types.yaml#/definitions/phandle-array 201 minItems: 1 202 maxItems: 4 203 items: 204 maxItems: 1 205 description: | 206 phandles to one or more reserved on-chip SRAM regions. The regions 207 should be defined as child nodes of the respective SRAM node, and 208 should be defined as per the generic bindings in, 209 Documentation/devicetree/bindings/sram/sram.yaml 210 211 required: 212 - compatible 213 - reg 214 - reg-names 215 - ti,sci 216 - ti,sci-dev-id 217 - ti,sci-proc-ids 218 - resets 219 - firmware-name 220 221 unevaluatedProperties: false 222 223allOf: 224 - if: 225 properties: 226 compatible: 227 enum: 228 - ti,am64-r5fss 229 then: 230 properties: 231 ti,cluster-mode: 232 enum: [0, 2] 233 234 - if: 235 properties: 236 compatible: 237 enum: 238 - ti,am654-r5fss 239 - ti,j7200-r5fss 240 - ti,j721e-r5fss 241 - ti,j721s2-r5fss 242 then: 243 properties: 244 ti,cluster-mode: 245 enum: [0, 1] 246 247 - if: 248 properties: 249 compatible: 250 enum: 251 - ti,am62-r5fss 252 then: 253 properties: 254 ti,cluster-mode: 255 enum: [3] 256 257required: 258 - compatible 259 - power-domains 260 - "#address-cells" 261 - "#size-cells" 262 - ranges 263 264additionalProperties: false 265 266examples: 267 - | 268 soc { 269 #address-cells = <2>; 270 #size-cells = <2>; 271 272 mailbox0: mailbox-0 { 273 #mbox-cells = <1>; 274 }; 275 276 mailbox1: mailbox-1 { 277 #mbox-cells = <1>; 278 }; 279 280 bus@100000 { 281 compatible = "simple-bus"; 282 #address-cells = <2>; 283 #size-cells = <2>; 284 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ 285 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, 286 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, 287 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; 288 289 bus@28380000 { 290 compatible = "simple-bus"; 291 #address-cells = <2>; 292 #size-cells = <2>; 293 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS */ 294 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ 295 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ 296 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */ 297 298 /* AM65x MCU R5FSS node */ 299 mcu_r5fss0: r5fss@41000000 { 300 compatible = "ti,am654-r5fss"; 301 power-domains = <&k3_pds 129>; 302 ti,cluster-mode = <1>; 303 #address-cells = <1>; 304 #size-cells = <1>; 305 ranges = <0x41000000 0x00 0x41000000 0x20000>, 306 <0x41400000 0x00 0x41400000 0x20000>; 307 308 mcu_r5f0: r5f@41000000 { 309 compatible = "ti,am654-r5f"; 310 reg = <0x41000000 0x00008000>, 311 <0x41010000 0x00008000>; 312 reg-names = "atcm", "btcm"; 313 ti,sci = <&dmsc>; 314 ti,sci-dev-id = <159>; 315 ti,sci-proc-ids = <0x01 0xFF>; 316 resets = <&k3_reset 159 1>; 317 firmware-name = "am65x-mcu-r5f0_0-fw"; 318 ti,atcm-enable = <1>; 319 ti,btcm-enable = <1>; 320 ti,loczrama = <1>; 321 mboxes = <&mailbox0 &mbox_mcu_r5fss0_core0>; 322 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 323 <&mcu_r5fss0_core0_memory_region>; 324 sram = <&mcu_r5fss0_core0_sram>; 325 }; 326 327 mcu_r5f1: r5f@41400000 { 328 compatible = "ti,am654-r5f"; 329 reg = <0x41400000 0x00008000>, 330 <0x41410000 0x00008000>; 331 reg-names = "atcm", "btcm"; 332 ti,sci = <&dmsc>; 333 ti,sci-dev-id = <245>; 334 ti,sci-proc-ids = <0x02 0xFF>; 335 resets = <&k3_reset 245 1>; 336 firmware-name = "am65x-mcu-r5f0_1-fw"; 337 ti,atcm-enable = <1>; 338 ti,btcm-enable = <1>; 339 ti,loczrama = <1>; 340 mboxes = <&mailbox1 &mbox_mcu_r5fss0_core1>; 341 }; 342 }; 343 }; 344 }; 345 };
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