qcom,sdm845-adsp-pil.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/remoteproc/qcom,sdm845-adsp-pil.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm SDM845 ADSP Peripheral Image Loader
  8
  9maintainers:
 10  - Bjorn Andersson <bjorn.andersson@linaro.org>
 11
 12description:
 13  This document defines the binding for a component that loads and boots firmware
 14  on the Qualcomm Technology Inc. ADSP.
 15
 16properties:
 17  compatible:
 18    enum:
 19      - qcom,sdm845-adsp-pil
 20
 21  reg:
 22    maxItems: 1
 23    description:
 24      The base address and size of the qdsp6ss register
 25
 26  interrupts:
 27    items:
 28      - description: Watchdog interrupt
 29      - description: Fatal interrupt
 30      - description: Ready interrupt
 31      - description: Handover interrupt
 32      - description: Stop acknowledge interrupt
 33
 34  interrupt-names:
 35    items:
 36      - const: wdog
 37      - const: fatal
 38      - const: ready
 39      - const: handover
 40      - const: stop-ack
 41
 42  clocks:
 43    items:
 44      - description: XO clock
 45      - description: SWAY clock
 46      - description: LPASS AHBS AON clock
 47      - description: LPASS AHBM AON clock
 48      - description: QDSP XO clock
 49      - description: Q6SP6SS SLEEP clock
 50      - description: Q6SP6SS CORE clock
 51
 52  clock-names:
 53    items:
 54      - const: xo
 55      - const: sway_cbcr
 56      - const: lpass_ahbs_aon_cbcr
 57      - const: lpass_ahbm_aon_cbcr
 58      - const: qdsp6ss_xo
 59      - const: qdsp6ss_sleep
 60      - const: qdsp6ss_core
 61
 62  power-domains:
 63    items:
 64      - description: CX power domain
 65
 66  resets:
 67    items:
 68      - description: PDC AUDIO SYNC RESET
 69      - description: CC LPASS restart
 70
 71  reset-names:
 72    items:
 73      - const: pdc_sync
 74      - const: cc_lpass
 75
 76  memory-region:
 77    maxItems: 1
 78    description: Reference to the reserved-memory for the Hexagon core
 79
 80  qcom,halt-regs:
 81    $ref: /schemas/types.yaml#/definitions/phandle-array
 82    description:
 83      Phandle reference to a syscon representing TCSR followed by the
 84      offset within syscon for q6 halt register.
 85    items:
 86      - items:
 87          - description: phandle to TCSR syscon region
 88          - description: offset to the Q6 halt register
 89
 90  qcom,smem-states:
 91    $ref: /schemas/types.yaml#/definitions/phandle-array
 92    description: States used by the AP to signal the Hexagon core
 93    items:
 94      - description: Stop the modem
 95
 96  qcom,smem-state-names:
 97    description: The names of the state bits used for SMP2P output
 98    items:
 99      - const: stop
100
101required:
102  - compatible
103  - reg
104  - interrupts
105  - interrupt-names
106  - clocks
107  - clock-names
108  - power-domains
109  - resets
110  - reset-names
111  - qcom,halt-regs
112  - memory-region
113  - qcom,smem-states
114  - qcom,smem-state-names
115
116additionalProperties: false
117
118examples:
119  - |
120    #include <dt-bindings/interrupt-controller/arm-gic.h>
121    #include <dt-bindings/clock/qcom,rpmh.h>
122    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
123    #include <dt-bindings/clock/qcom,lpass-sdm845.h>
124    #include <dt-bindings/power/qcom-rpmpd.h>
125    #include <dt-bindings/reset/qcom,sdm845-pdc.h>
126    #include <dt-bindings/reset/qcom,sdm845-aoss.h>
127    remoteproc@17300000 {
128        compatible = "qcom,sdm845-adsp-pil";
129        reg = <0x17300000 0x40c>;
130
131        interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
132                <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
133                <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
134                <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
135                <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
136        interrupt-names = "wdog", "fatal", "ready",
137                "handover", "stop-ack";
138
139        clocks = <&rpmhcc RPMH_CXO_CLK>,
140                 <&gcc GCC_LPASS_SWAY_CLK>,
141                 <&lpasscc LPASS_Q6SS_AHBS_AON_CLK>,
142                 <&lpasscc LPASS_Q6SS_AHBM_AON_CLK>,
143                 <&lpasscc LPASS_QDSP6SS_XO_CLK>,
144                 <&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
145                 <&lpasscc LPASS_QDSP6SS_CORE_CLK>;
146        clock-names = "xo", "sway_cbcr",
147                "lpass_ahbs_aon_cbcr",
148                "lpass_ahbm_aon_cbcr", "qdsp6ss_xo",
149                "qdsp6ss_sleep", "qdsp6ss_core";
150
151        power-domains = <&rpmhpd SDM845_CX>;
152
153        resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,
154                 <&aoss_reset AOSS_CC_LPASS_RESTART>;
155        reset-names = "pdc_sync", "cc_lpass";
156
157        qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;
158
159        memory-region = <&pil_adsp_mem>;
160
161        qcom,smem-states = <&adsp_smp2p_out 0>;
162        qcom,smem-state-names = "stop";
163    };