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renesas,rzg2l-gpt.yaml
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linux-6.19.14/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pwm/renesas,rzg2l-gpt.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas RZ/G2L General PWM Timer (GPT) 8 9maintainers: 10 - Biju Das <biju.das.jz@bp.renesas.com> 11 12description: | 13 RZ/G2L General PWM Timer (GPT) composed of 8 channels with 32-bit timer 14 (GPT32E). It supports the following functions 15 * 32 bits x 8 channels. 16 * Up-counting or down-counting (saw waves) or up/down-counting 17 (triangle waves) for each counter. 18 * Clock sources independently selectable for each channel. 19 * Two I/O pins per channel. 20 * Two output compare/input capture registers per channel. 21 * For the two output compare/input capture registers of each channel, 22 four registers are provided as buffer registers and are capable of 23 operating as comparison registers when buffering is not in use. 24 * In output compare operation, buffer switching can be at crests or 25 troughs, enabling the generation of laterally asymmetric PWM waveforms. 26 * Registers for setting up frame cycles in each channel (with capability 27 for generating interrupts at overflow or underflow) 28 * Generation of dead times in PWM operation. 29 * Synchronous starting, stopping and clearing counters for arbitrary 30 channels. 31 * Starting, stopping, clearing and up/down counters in response to input 32 level comparison. 33 * Starting, clearing, stopping and up/down counters in response to a 34 maximum of four external triggers. 35 * Output pin disable function by dead time error and detected 36 short-circuits between output pins. 37 * A/D converter start triggers can be generated (GPT32E0 to GPT32E3) 38 * Enables the noise filter for input capture and external trigger 39 operation. 40 41 The below pwm channels are supported. 42 pwm0 - GPT32E0.GTIOC0A channel 43 pwm1 - GPT32E0.GTIOC0B channel 44 pwm2 - GPT32E1.GTIOC1A channel 45 pwm3 - GPT32E1.GTIOC1B channel 46 pwm4 - GPT32E2.GTIOC2A channel 47 pwm5 - GPT32E2.GTIOC2B channel 48 pwm6 - GPT32E3.GTIOC3A channel 49 pwm7 - GPT32E3.GTIOC3B channel 50 pwm8 - GPT32E4.GTIOC4A channel 51 pwm9 - GPT32E4.GTIOC4B channel 52 pwm10 - GPT32E5.GTIOC5A channel 53 pwm11 - GPT32E5.GTIOC5B channel 54 pwm12 - GPT32E6.GTIOC6A channel 55 pwm13 - GPT32E6.GTIOC6B channel 56 pwm14 - GPT32E7.GTIOC7A channel 57 pwm15 - GPT32E7.GTIOC7B channel 58 59properties: 60 compatible: 61 items: 62 - enum: 63 - renesas,r9a07g044-gpt # RZ/G2{L,LC} 64 - renesas,r9a07g054-gpt # RZ/V2L 65 - const: renesas,rzg2l-gpt 66 67 reg: 68 maxItems: 1 69 70 '#pwm-cells': 71 const: 3 72 73 interrupts: 74 items: 75 - description: GPT32E0.GTCCRA input capture/compare match 76 - description: GPT32E0.GTCCRB input capture/compare 77 - description: GPT32E0.GTCCRC compare match 78 - description: GPT32E0.GTCCRD compare match 79 - description: GPT32E0.GTCCRE compare match 80 - description: GPT32E0.GTCCRF compare match 81 - description: GPT32E0.GTADTRA compare match 82 - description: GPT32E0.GTADTRB compare match 83 - description: GPT32E0.GTCNT overflow/GTPR compare match 84 - description: GPT32E0.GTCNT underflow 85 - description: GPT32E1.GTCCRA input capture/compare match 86 - description: GPT32E1.GTCCRB input capture/compare 87 - description: GPT32E1.GTCCRC compare match 88 - description: GPT32E1.GTCCRD compare match 89 - description: GPT32E1.GTCCRE compare match 90 - description: GPT32E1.GTCCRF compare match 91 - description: GPT32E1.GTADTRA compare match 92 - description: GPT32E1.GTADTRB compare match 93 - description: GPT32E1.GTCNT overflow/GTPR compare match 94 - description: GPT32E1.GTCNT underflow 95 - description: GPT32E2.GTCCRA input capture/compare match 96 - description: GPT32E2.GTCCRB input capture/compare 97 - description: GPT32E2.GTCCRC compare match 98 - description: GPT32E2.GTCCRD compare match 99 - description: GPT32E2.GTCCRE compare match 100 - description: GPT32E2.GTCCRF compare match 101 - description: GPT32E2.GTADTRA compare match 102 - description: GPT32E2.GTADTRB compare match 103 - description: GPT32E2.GTCNT overflow/GTPR compare match 104 - description: GPT32E2.GTCNT underflow 105 - description: GPT32E3.GTCCRA input capture/compare match 106 - description: GPT32E3.GTCCRB input capture/compare 107 - description: GPT32E3.GTCCRC compare match 108 - description: GPT32E3.GTCCRD compare match 109 - description: GPT32E3.GTCCRE compare match 110 - description: GPT32E3.GTCCRF compare match 111 - description: GPT32E3.GTADTRA compare match 112 - description: GPT32E3.GTADTRB compare match 113 - description: GPT32E3.GTCNT overflow/GTPR compare match 114 - description: GPT32E3.GTCNT underflow 115 - description: GPT32E4.GTCCRA input capture/compare match 116 - description: GPT32E4.GTCCRB input capture/compare 117 - description: GPT32E4.GTCCRC compare match 118 - description: GPT32E4.GTCCRD compare match 119 - description: GPT32E4.GTCCRE compare match 120 - description: GPT32E4.GTCCRF compare match 121 - description: GPT32E4.GTADTRA compare match 122 - description: GPT32E4.GTADTRB compare match 123 - description: GPT32E4.GTCNT overflow/GTPR compare match 124 - description: GPT32E4.GTCNT underflow 125 - description: GPT32E5.GTCCRA input capture/compare match 126 - description: GPT32E5.GTCCRB input capture/compare 127 - description: GPT32E5.GTCCRC compare match 128 - description: GPT32E5.GTCCRD compare match 129 - description: GPT32E5.GTCCRE compare match 130 - description: GPT32E5.GTCCRF compare match 131 - description: GPT32E5.GTADTRA compare match 132 - description: GPT32E5.GTADTRB compare match 133 - description: GPT32E5.GTCNT overflow/GTPR compare match 134 - description: GPT32E5.GTCNT underflow 135 - description: GPT32E6.GTCCRA input capture/compare match 136 - description: GPT32E6.GTCCRB input capture/compare 137 - description: GPT32E6.GTCCRC compare match 138 - description: GPT32E6.GTCCRD compare match 139 - description: GPT32E6.GTCCRE compare match 140 - description: GPT32E6.GTCCRF compare match 141 - description: GPT32E6.GTADTRA compare match 142 - description: GPT32E6.GTADTRB compare match 143 - description: GPT32E6.GTCNT overflow/GTPR compare match 144 - description: GPT32E6.GTCNT underflow 145 - description: GPT32E7.GTCCRA input capture/compare match 146 - description: GPT32E7.GTCCRB input capture/compare 147 - description: GPT32E7.GTCCRC compare match 148 - description: GPT32E7.GTCCRD compare match 149 - description: GPT32E7.GTCCRE compare match 150 - description: GPT32E7.GTCCRF compare match 151 - description: GPT32E7.GTADTRA compare match 152 - description: GPT32E7.GTADTRB compare match 153 - description: GPT32E7.GTCNT overflow/GTPR compare match 154 - description: GPT32E7.GTCNT underflow 155 156 interrupt-names: 157 items: 158 - const: ccmpa0 159 - const: ccmpb0 160 - const: cmpc0 161 - const: cmpd0 162 - const: cmpe0 163 - const: cmpf0 164 - const: adtrga0 165 - const: adtrgb0 166 - const: ovf0 167 - const: unf0 168 - const: ccmpa1 169 - const: ccmpb1 170 - const: cmpc1 171 - const: cmpd1 172 - const: cmpe1 173 - const: cmpf1 174 - const: adtrga1 175 - const: adtrgb1 176 - const: ovf1 177 - const: unf1 178 - const: ccmpa2 179 - const: ccmpb2 180 - const: cmpc2 181 - const: cmpd2 182 - const: cmpe2 183 - const: cmpf2 184 - const: adtrga2 185 - const: adtrgb2 186 - const: ovf2 187 - const: unf2 188 - const: ccmpa3 189 - const: ccmpb3 190 - const: cmpc3 191 - const: cmpd3 192 - const: cmpe3 193 - const: cmpf3 194 - const: adtrga3 195 - const: adtrgb3 196 - const: ovf3 197 - const: unf3 198 - const: ccmpa4 199 - const: ccmpb4 200 - const: cmpc4 201 - const: cmpd4 202 - const: cmpe4 203 - const: cmpf4 204 - const: adtrga4 205 - const: adtrgb4 206 - const: ovf4 207 - const: unf4 208 - const: ccmpa5 209 - const: ccmpb5 210 - const: cmpc5 211 - const: cmpd5 212 - const: cmpe5 213 - const: cmpf5 214 - const: adtrga5 215 - const: adtrgb5 216 - const: ovf5 217 - const: unf5 218 - const: ccmpa6 219 - const: ccmpb6 220 - const: cmpc6 221 - const: cmpd6 222 - const: cmpe6 223 - const: cmpf6 224 - const: adtrga6 225 - const: adtrgb6 226 - const: ovf6 227 - const: unf6 228 - const: ccmpa7 229 - const: ccmpb7 230 - const: cmpc7 231 - const: cmpd7 232 - const: cmpe7 233 - const: cmpf7 234 - const: adtrga7 235 - const: adtrgb7 236 - const: ovf7 237 - const: unf7 238 239 clocks: 240 maxItems: 1 241 242 power-domains: 243 maxItems: 1 244 245 resets: 246 maxItems: 1 247 248required: 249 - compatible 250 - reg 251 - interrupts 252 - interrupt-names 253 - clocks 254 - power-domains 255 - resets 256 257allOf: 258 - $ref: pwm.yaml# 259 260additionalProperties: false 261 262examples: 263 - | 264 #include <dt-bindings/clock/r9a07g044-cpg.h> 265 #include <dt-bindings/interrupt-controller/arm-gic.h> 266 267 gpt: pwm@10048000 { 268 compatible = "renesas,r9a07g044-gpt", "renesas,rzg2l-gpt"; 269 reg = <0x10048000 0x800>; 270 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>, 271 <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>, 272 <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>, 273 <GIC_SPI 221 IRQ_TYPE_EDGE_RISING>, 274 <GIC_SPI 222 IRQ_TYPE_EDGE_RISING>, 275 <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>, 276 <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>, 277 <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>, 278 <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>, 279 <GIC_SPI 227 IRQ_TYPE_EDGE_RISING>, 280 <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>, 281 <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>, 282 <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>, 283 <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>, 284 <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>, 285 <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>, 286 <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>, 287 <GIC_SPI 238 IRQ_TYPE_EDGE_RISING>, 288 <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>, 289 <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>, 290 <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>, 291 <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>, 292 <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>, 293 <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>, 294 <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>, 295 <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>, 296 <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 297 <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>, 298 <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>, 299 <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>, 300 <GIC_SPI 257 IRQ_TYPE_EDGE_RISING>, 301 <GIC_SPI 258 IRQ_TYPE_EDGE_RISING>, 302 <GIC_SPI 259 IRQ_TYPE_EDGE_RISING>, 303 <GIC_SPI 260 IRQ_TYPE_EDGE_RISING>, 304 <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>, 305 <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, 306 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 307 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 308 <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 309 <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 310 <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>, 311 <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>, 312 <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>, 313 <GIC_SPI 273 IRQ_TYPE_EDGE_RISING>, 314 <GIC_SPI 274 IRQ_TYPE_EDGE_RISING>, 315 <GIC_SPI 275 IRQ_TYPE_EDGE_RISING>, 316 <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>, 317 <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>, 318 <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>, 319 <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>, 320 <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>, 321 <GIC_SPI 284 IRQ_TYPE_EDGE_RISING>, 322 <GIC_SPI 285 IRQ_TYPE_EDGE_RISING>, 323 <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>, 324 <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>, 325 <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>, 326 <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>, 327 <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>, 328 <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>, 329 <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>, 330 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 331 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 332 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 333 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 334 <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>, 335 <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>, 336 <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>, 337 <GIC_SPI 303 IRQ_TYPE_EDGE_RISING>, 338 <GIC_SPI 304 IRQ_TYPE_EDGE_RISING>, 339 <GIC_SPI 305 IRQ_TYPE_EDGE_RISING>, 340 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 341 <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>, 342 <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 343 <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>, 344 <GIC_SPI 313 IRQ_TYPE_EDGE_RISING>, 345 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 346 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>, 347 <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>, 348 <GIC_SPI 317 IRQ_TYPE_EDGE_RISING>, 349 <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 350 interrupt-names = "ccmpa0", "ccmpb0", "cmpc0", "cmpd0", 351 "cmpe0", "cmpf0", "adtrga0", "adtrgb0", 352 "ovf0", "unf0", 353 "ccmpa1", "ccmpb1", "cmpc1", "cmpd1", 354 "cmpe1", "cmpf1", "adtrga1", "adtrgb1", 355 "ovf1", "unf1", 356 "ccmpa2", "ccmpb2", "cmpc2", "cmpd2", 357 "cmpe2", "cmpf2", "adtrga2", "adtrgb2", 358 "ovf2", "unf2", 359 "ccmpa3", "ccmpb3", "cmpc3", "cmpd3", 360 "cmpe3", "cmpf3", "adtrga3", "adtrgb3", 361 "ovf3", "unf3", 362 "ccmpa4", "ccmpb4", "cmpc4", "cmpd4", 363 "cmpe4", "cmpf4", "adtrga4", "adtrgb4", 364 "ovf4", "unf4", 365 "ccmpa5", "ccmpb5", "cmpc5", "cmpd5", 366 "cmpe5", "cmpf5", "adtrga5", "adtrgb5", 367 "ovf5", "unf5", 368 "ccmpa6", "ccmpb6", "cmpc6", "cmpd6", 369 "cmpe6", "cmpf6", "adtrga6", "adtrgb6", 370 "ovf6", "unf6", 371 "ccmpa7", "ccmpb7", "cmpc7", "cmpd7", 372 "cmpe7", "cmpf7", "adtrga7", "adtrgb7", 373 "ovf7", "unf7"; 374 clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>; 375 power-domains = <&cpg>; 376 resets = <&cpg R9A07G044_GPT_RST_C>; 377 #pwm-cells = <3>; 378 };
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