mediatek,mt2712-pwm.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pwm/mediatek,mt2712-pwm.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: MediaTek PWM Controller
  8
  9maintainers:
 10  - John Crispin <john@phrozen.org>
 11
 12allOf:
 13  - $ref: pwm.yaml#
 14
 15properties:
 16  compatible:
 17    oneOf:
 18      - enum:
 19          - mediatek,mt2712-pwm
 20          - mediatek,mt6795-pwm
 21          - mediatek,mt6991-pwm
 22          - mediatek,mt7622-pwm
 23          - mediatek,mt7623-pwm
 24          - mediatek,mt7628-pwm
 25          - mediatek,mt7629-pwm
 26          - mediatek,mt7981-pwm
 27          - mediatek,mt7986-pwm
 28          - mediatek,mt7988-pwm
 29          - mediatek,mt8183-pwm
 30          - mediatek,mt8365-pwm
 31          - mediatek,mt8516-pwm
 32      - items:
 33          - enum:
 34              - mediatek,mt8195-pwm
 35          - const: mediatek,mt8183-pwm
 36      - items:
 37          - enum:
 38              - mediatek,mt8196-pwm
 39          - const: mediatek,mt6991-pwm
 40
 41  reg:
 42    maxItems: 1
 43
 44  "#pwm-cells":
 45    const: 2
 46
 47  interrupts:
 48    maxItems: 1
 49
 50  clocks:
 51    minItems: 2
 52    maxItems: 10
 53
 54  clock-names:
 55    description:
 56      This controller needs two input clocks for its core and one
 57      clock for each PWM output.
 58    minItems: 2
 59    items:
 60      - const: top
 61      - const: main
 62      - const: pwm1
 63      - const: pwm2
 64      - const: pwm3
 65      - const: pwm4
 66      - const: pwm5
 67      - const: pwm6
 68      - const: pwm7
 69      - const: pwm8
 70
 71required:
 72  - compatible
 73  - reg
 74  - clocks
 75  - clock-names
 76
 77additionalProperties: false
 78
 79examples:
 80  - |
 81    #include <dt-bindings/interrupt-controller/arm-gic.h>
 82    #include <dt-bindings/clock/mt2712-clk.h>
 83    #include <dt-bindings/interrupt-controller/irq.h>
 84
 85    pwm0: pwm@11006000 {
 86        compatible = "mediatek,mt2712-pwm";
 87        reg = <0x11006000 0x1000>;
 88        #pwm-cells = <2>;
 89        interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 90        clocks = <&topckgen CLK_TOP_PWM_SEL>, <&pericfg CLK_PERI_PWM>,
 91                 <&pericfg CLK_PERI_PWM0>, <&pericfg CLK_PERI_PWM1>,
 92                 <&pericfg CLK_PERI_PWM2>, <&pericfg CLK_PERI_PWM3>,
 93                 <&pericfg CLK_PERI_PWM4>, <&pericfg CLK_PERI_PWM5>,
 94                 <&pericfg CLK_PERI_PWM6>, <&pericfg CLK_PERI_PWM7>;
 95        clock-names = "top", "main",
 96                      "pwm1", "pwm2",
 97                      "pwm3", "pwm4",
 98                      "pwm5", "pwm6",
 99                      "pwm7", "pwm8";
100    };