mpc5200.txt

  1MPC5200 Device Tree Bindings
  2----------------------------
  3
  4(c) 2006-2009 Secret Lab Technologies Ltd
  5Grant Likely <grant.likely@secretlab.ca>
  6
  7Naming conventions
  8------------------
  9For mpc5200 on-chip devices, the format for each compatible value is
 10<chip>-<device>[-<mode>].  The OS should be able to match a device driver
 11to the device based solely on the compatible value.  If two drivers
 12match on the compatible list; the 'most compatible' driver should be
 13selected.
 14
 15The split between the MPC5200 and the MPC5200B leaves a bit of a
 16conundrum.  How should the compatible property be set up to provide
 17maximum compatibility information; but still accurately describe the
 18chip?  For the MPC5200; the answer is easy.  Most of the SoC devices
 19originally appeared on the MPC5200.  Since they didn't exist anywhere
 20else; the 5200 compatible properties will contain only one item;
 21"fsl,mpc5200-<device>".
 22
 23The 5200B is almost the same as the 5200, but not quite.  It fixes
 24silicon bugs and it adds a small number of enhancements.  Most of the
 25devices either provide exactly the same interface as on the 5200.  A few
 26devices have extra functions but still have a backwards compatible mode.
 27To express this information as completely as possible, 5200B device trees
 28should have two items in the compatible list:
 29	compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
 30
 31It is *strongly* recommended that 5200B device trees follow this convention
 32(instead of only listing the base mpc5200 item).
 33
 34ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
 35    ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
 36
 37Modal devices, like PSCs, also append the configured function to the
 38end of the compatible field.  ie. A PSC in i2s mode would specify
 39"fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s".  This convention is chosen to
 40avoid naming conflicts with non-psc devices providing the same
 41function.  For example, "fsl,mpc5200-spi" and "fsl,mpc5200-psc-spi" describe
 42the mpc5200 simple spi device and a PSC spi mode respectively.
 43
 44At the time of writing, exact chip may be either 'fsl,mpc5200' or
 45'fsl,mpc5200b'.
 46
 47The soc node
 48------------
 49This node describes the on chip SOC peripherals.  Every mpc5200 based
 50board will have this node, and as such there is a common naming
 51convention for SOC devices.
 52
 53Required properties:
 54name			description
 55----			-----------
 56ranges			Memory range of the internal memory mapped registers.
 57			Should be <0 [baseaddr] 0xc000>
 58reg			Should be <[baseaddr] 0x100>
 59compatible		mpc5200: "fsl,mpc5200-immr"
 60			mpc5200b: "fsl,mpc5200b-immr"
 61system-frequency	'fsystem' frequency in Hz; XLB, IPB, USB and PCI
 62			clocks are derived from the fsystem clock.
 63bus-frequency		IPB bus frequency in Hz.  Clock rate
 64			used by most of the soc devices.
 65
 66soc child nodes
 67---------------
 68Any on chip SOC devices available to Linux must appear as soc5200 child nodes.
 69
 70Note: The tables below show the value for the mpc5200.  A mpc5200b device
 71tree should use the "fsl,mpc5200b-<device>","fsl,mpc5200-<device>" form.
 72
 73Required soc5200 child nodes:
 74name				compatible		Description
 75----				----------		-----------
 76cdm@<addr>			fsl,mpc5200-cdm		Clock Distribution
 77interrupt-controller@<addr>	fsl,mpc5200-pic		need an interrupt
 78							controller to boot
 79bestcomm@<addr>			fsl,mpc5200-bestcomm	Bestcomm DMA controller
 80
 81Recommended soc5200 child nodes; populate as needed for your board
 82name		compatible		Description
 83----		----------		-----------
 84timer@<addr>	fsl,mpc5200-gpt		 General purpose timers
 85gpio@<addr>	fsl,mpc5200-gpio	 MPC5200 simple gpio controller
 86gpio@<addr>	fsl,mpc5200-gpio-wkup	 MPC5200 wakeup gpio controller
 87rtc@<addr>	fsl,mpc5200-rtc		 Real time clock
 88mscan@<addr>	fsl,mpc5200-mscan	 CAN bus controller
 89pci@<addr>	fsl,mpc5200-pci		 PCI bridge
 90serial@<addr>	fsl,mpc5200-psc-uart	 PSC in serial mode
 91i2s@<addr>	fsl,mpc5200-psc-i2s	 PSC in i2s mode
 92ac97@<addr>	fsl,mpc5200-psc-ac97	 PSC in ac97 mode
 93spi@<addr>	fsl,mpc5200-psc-spi	 PSC in spi mode
 94irda@<addr>	fsl,mpc5200-psc-irda	 PSC in IrDA mode
 95spi@<addr>	fsl,mpc5200-spi		 MPC5200 spi device
 96ethernet@<addr>	fsl,mpc5200-fec		 MPC5200 ethernet device
 97ata@<addr>	fsl,mpc5200-ata		 IDE ATA interface
 98i2c@<addr>	fsl,mpc5200-i2c		 I2C controller
 99usb@<addr>	fsl,mpc5200-ohci,ohci-be USB controller
100xlb@<addr>	fsl,mpc5200-xlb		 XLB arbitrator
101
102fsl,mpc5200-gpt nodes
103---------------------
104On the mpc5200 and 5200b, GPT0 has a watchdog timer function.  If the board
105design supports the internal wdt, then the device node for GPT0 should
106include the empty property 'fsl,has-wdt'.  Note that this does not activate
107the watchdog.  The timer will function as a GPT if the timer api is used, and
108it will function as watchdog if the watchdog device is used.  The watchdog
109mode has priority over the gpt mode, i.e. if the watchdog is activated, any
110gpt api call to this timer will fail with -EBUSY.
111
112If you add the property
113	fsl,wdt-on-boot = <n>;
114GPT0 will be marked as in-use watchdog, i.e. blocking every gpt access to it.
115If n>0, the watchdog is started with a timeout of n seconds.  If n=0, the
116configuration of the watchdog is not touched.  This is useful in two cases:
117- just mark GPT0 as watchdog, blocking gpt accesses, and configure it later;
118- do not touch a configuration assigned by the boot loader which supervises
119  the boot process itself.
120
121The watchdog will respect the CONFIG_WATCHDOG_NOWAYOUT option.
122
123An mpc5200-gpt can be used as a single line GPIO controller.  To do so,
124add the following properties to the gpt node:
125	gpio-controller;
126	#gpio-cells = <2>;
127When referencing the GPIO line from another node, the first cell must always
128be zero and the second cell represents the gpio flags and described in the
129gpio device tree binding.
130
131An mpc5200-gpt can be used as a single line edge sensitive interrupt
132controller.  To do so, add the following properties to the gpt node:
133	interrupt-controller;
134	#interrupt-cells = <1>;
135When referencing the IRQ line from another node, the cell represents the
136sense mode; 1 for edge rising, 2 for edge falling.
137
138fsl,mpc5200-psc nodes
139---------------------
140The PSCs should include a cell-index which is the index of the PSC in
141hardware.  cell-index is used to determine which shared SoC registers to
142use when setting up PSC clocking.  cell-index number starts at '0'.  ie:
143	PSC1 has 'cell-index = <0>'
144	PSC4 has 'cell-index = <3>'
145
146PSC in i2s mode:  The mpc5200 and mpc5200b PSCs are not compatible when in
147i2s mode.  An 'mpc5200b-psc-i2s' node cannot include 'mpc5200-psc-i2s' in the
148compatible field.
149
150
151fsl,mpc5200-gpio and fsl,mpc5200-gpio-wkup nodes
152------------------------------------------------
153Each GPIO controller node should have the empty property gpio-controller and
154#gpio-cells set to 2. First cell is the GPIO number which is interpreted
155according to the bit numbers in the GPIO control registers. The second cell
156is for flags which is currently unused.
157
158fsl,mpc5200-fec nodes
159---------------------
160The FEC node can specify one of the following properties to configure
161the MII link:
162- fsl,7-wire-mode - An empty property that specifies the link uses 7-wire
163                    mode instead of MII
164- current-speed   - Specifies that the MII should be configured for a fixed
165                    speed.  This property should contain two cells.  The
166                    first cell specifies the speed in Mbps and the second
167                    should be '0' for half duplex and '1' for full duplex
168- phy-handle      - Contains a phandle to an Ethernet PHY.
169
170Interrupt controller (fsl,mpc5200-pic) node
171-------------------------------------------
172The mpc5200 pic binding splits hardware IRQ numbers into two levels.  The
173split reflects the layout of the PIC hardware itself, which groups
174interrupts into one of three groups; CRIT, MAIN or PERP.  Also, the
175Bestcomm dma engine has its own set of interrupt sources which are
176cascaded off of peripheral interrupt 0, which the driver interprets as a
177fourth group, SDMA.
178
179The interrupts property for device nodes using the mpc5200 pic consists
180of three cells; <L1 L2 level>
181
182    L1 := [CRIT=0, MAIN=1, PERP=2, SDMA=3]
183    L2 := interrupt number; directly mapped from the value in the
184          "ICTL PerStat, MainStat, CritStat Encoded Register"
185    level := [LEVEL_HIGH=0, EDGE_RISING=1, EDGE_FALLING=2, LEVEL_LOW=3]
186
187For external IRQs, use the following interrupt property values (how to
188specify external interrupts is a frequently asked question):
189External interrupts:
190	external irq0:	interrupts = <0 0 n>;
191	external irq1:	interrupts = <1 1 n>;
192	external irq2:	interrupts = <1 2 n>;
193	external irq3:	interrupts = <1 3 n>;
194'n' is sense (0: level high, 1: edge rising, 2: edge falling 3: level low)
195
196fsl,mpc5200-mscan nodes
197-----------------------
198See file Documentation/devicetree/bindings/powerpc/fsl/mpc5200.txt