ocelot-reset.txt

 1Microsemi Ocelot reset controller
 2
 3The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
 4SoC core.
 5
 6The reset registers are both present in the MSCC vcoreiii MIPS and
 7microchip Sparx5 armv8 SoC's.
 8
 9Required Properties:
10
11 - compatible: "mscc,ocelot-chip-reset", "mscc,luton-chip-reset",
12   "mscc,jaguar2-chip-reset" or "microchip,sparx5-chip-reset"
13
14Example:
15	reset@1070008 {
16		compatible = "mscc,ocelot-chip-reset";
17		reg = <0x1070008 0x4>;
18	};
19