mediatek,mt8196-gpufreq.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/power/mediatek,mt8196-gpufreq.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: MediaTek MFlexGraphics Power and Frequency Controller
  8
  9maintainers:
 10  - Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
 11
 12description:
 13  A special-purpose embedded MCU to control power and frequency of GPU devices
 14  using MediaTek Flexible Graphics integration hardware.
 15
 16properties:
 17  $nodename:
 18    pattern: '^power-controller@[a-f0-9]+$'
 19
 20  compatible:
 21    enum:
 22      - mediatek,mt8196-gpufreq
 23
 24  reg:
 25    items:
 26      - description: GPR memory area
 27      - description: RPC memory area
 28      - description: SoC variant ID register
 29
 30  reg-names:
 31    items:
 32      - const: gpr
 33      - const: rpc
 34      - const: hw-revision
 35
 36  clocks:
 37    items:
 38      - description: main clock of the embedded controller (EB)
 39      - description: core PLL
 40      - description: stack 0 PLL
 41      - description: stack 1 PLL
 42
 43  clock-names:
 44    items:
 45      - const: eb
 46      - const: core
 47      - const: stack0
 48      - const: stack1
 49
 50  mboxes:
 51    items:
 52      - description: FastDVFS events
 53      - description: frequency control
 54      - description: sleep control
 55      - description: timer control
 56      - description: frequency hopping control
 57      - description: hardware voter control
 58      - description: FastDVFS control
 59
 60  mbox-names:
 61    items:
 62      - const: fast-dvfs-event
 63      - const: gpufreq
 64      - const: sleep
 65      - const: timer
 66      - const: fhctl
 67      - const: ccf
 68      - const: fast-dvfs
 69
 70  memory-region:
 71    items:
 72      - description: phandle to the GPUEB shared memory
 73
 74  "#clock-cells":
 75    const: 1
 76
 77  "#power-domain-cells":
 78    const: 0
 79
 80required:
 81  - compatible
 82  - reg
 83  - reg-names
 84  - clocks
 85  - clock-names
 86  - mboxes
 87  - mbox-names
 88  - memory-region
 89  - "#clock-cells"
 90  - "#power-domain-cells"
 91
 92additionalProperties: false
 93
 94examples:
 95  - |
 96    #include <dt-bindings/clock/mediatek,mt8196-clock.h>
 97
 98    power-controller@4b09fd00 {
 99        compatible = "mediatek,mt8196-gpufreq";
100        reg = <0x4b09fd00 0x80>,
101              <0x4b800000 0x1000>,
102              <0x4b860128 0x4>;
103        reg-names = "gpr", "rpc", "hw-revision";
104        clocks = <&topckgen CLK_TOP_MFG_EB>,
105                 <&mfgpll CLK_MFG_AO_MFGPLL>,
106                 <&mfgpll_sc0 CLK_MFGSC0_AO_MFGPLL_SC0>,
107                 <&mfgpll_sc1 CLK_MFGSC1_AO_MFGPLL_SC1>;
108        clock-names = "eb", "core", "stack0", "stack1";
109        mboxes = <&gpueb_mbox 0>, <&gpueb_mbox 1>, <&gpueb_mbox 2>,
110                 <&gpueb_mbox 3>, <&gpueb_mbox 4>, <&gpueb_mbox 5>,
111                 <&gpueb_mbox 7>;
112        mbox-names = "fast-dvfs-event", "gpufreq", "sleep", "timer", "fhctl",
113                     "ccf", "fast-dvfs";
114        memory-region = <&gpueb_shared_memory>;
115        #clock-cells = <1>;
116        #power-domain-cells = <0>;
117    };