rockchip,pinctrl.yaml

  1# SPDX-License-Identifier: GPL-2.0
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pinctrl/rockchip,pinctrl.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Rockchip Pinmux Controller
  8
  9maintainers:
 10  - Heiko Stuebner <heiko@sntech.de>
 11
 12description: |
 13  The Rockchip Pinmux Controller enables the IC to share one PAD
 14  to several functional blocks. The sharing is done by multiplexing
 15  the PAD input/output signals. For each PAD there are several muxing
 16  options with option 0 being used as a GPIO.
 17
 18  Please refer to pinctrl-bindings.txt in this directory for details of the
 19  common pinctrl bindings used by client devices, including the meaning of the
 20  phrase "pin configuration node".
 21
 22  The Rockchip pin configuration node is a node of a group of pins which can be
 23  used for a specific device or function. This node represents both mux and
 24  config of the pins in that group. The 'pins' selects the function mode
 25  (also named pin mode) this pin can work on and the 'config' configures
 26  various pad settings such as pull-up, etc.
 27
 28  The pins are grouped into up to 9 individual pin banks which need to be
 29  defined as gpio sub-nodes of the pinmux controller.
 30
 31properties:
 32  compatible:
 33    enum:
 34      - rockchip,px30-pinctrl
 35      - rockchip,rk2928-pinctrl
 36      - rockchip,rk3036-pinctrl
 37      - rockchip,rk3066a-pinctrl
 38      - rockchip,rk3066b-pinctrl
 39      - rockchip,rk3128-pinctrl
 40      - rockchip,rk3188-pinctrl
 41      - rockchip,rk3228-pinctrl
 42      - rockchip,rk3288-pinctrl
 43      - rockchip,rk3308-pinctrl
 44      - rockchip,rk3328-pinctrl
 45      - rockchip,rk3368-pinctrl
 46      - rockchip,rk3399-pinctrl
 47      - rockchip,rk3506-pinctrl
 48      - rockchip,rk3528-pinctrl
 49      - rockchip,rk3562-pinctrl
 50      - rockchip,rk3568-pinctrl
 51      - rockchip,rk3576-pinctrl
 52      - rockchip,rk3588-pinctrl
 53      - rockchip,rv1108-pinctrl
 54      - rockchip,rv1126-pinctrl
 55
 56  rockchip,grf:
 57    $ref: /schemas/types.yaml#/definitions/phandle
 58    description:
 59      The phandle of the syscon node for the GRF registers.
 60
 61  rockchip,pmu:
 62    $ref: /schemas/types.yaml#/definitions/phandle
 63    description:
 64      The phandle of the syscon node for the PMU registers,
 65      as some SoCs carry parts of the iomux controller registers there.
 66      Required for at least rk3188 and rk3288. On the rk3368 this should
 67      point to the PMUGRF syscon.
 68
 69  "#address-cells":
 70    enum: [1, 2]
 71
 72  "#size-cells":
 73    enum: [1, 2]
 74
 75  ranges: true
 76
 77allOf:
 78  - $ref: pinctrl.yaml#
 79
 80required:
 81  - compatible
 82  - rockchip,grf
 83
 84patternProperties:
 85  "gpio@[0-9a-f]+$":
 86    type: object
 87
 88    $ref: /schemas/gpio/rockchip,gpio-bank.yaml#
 89    deprecated: true
 90
 91    unevaluatedProperties: false
 92
 93  "pcfg-[a-z0-9-]+$":
 94    type: object
 95    properties:
 96      bias-disable: true
 97
 98      bias-pull-down: true
 99
100      bias-pull-pin-default: true
101
102      bias-pull-up: true
103
104      drive-strength:
105        minimum: 0
106        maximum: 20
107
108      input-enable: true
109
110      input-schmitt-enable: true
111
112      output-high: true
113
114      output-low: true
115
116    additionalProperties: false
117
118additionalProperties:
119  type: object
120  additionalProperties:
121    type: object
122    additionalProperties: false
123
124    properties:
125      rockchip,pins:
126        $ref: /schemas/types.yaml#/definitions/uint32-matrix
127        minItems: 1
128        items:
129          items:
130            - minimum: 0
131              maximum: 8
132              description:
133                Pin bank.
134            - minimum: 0
135              maximum: 31
136              description:
137                Pin bank index.
138            - minimum: 0
139              maximum: 14
140              description:
141                Mux 0 means GPIO and mux 1 to N means
142                the specific device function.
143            - description:
144                The phandle of a node contains the generic pinconfig options
145                to use as described in pinctrl-bindings.txt.
146
147examples:
148  - |
149    #include <dt-bindings/interrupt-controller/arm-gic.h>
150    #include <dt-bindings/pinctrl/rockchip.h>
151
152    pinctrl: pinctrl {
153      compatible = "rockchip,rk3066a-pinctrl";
154      rockchip,grf = <&grf>;
155
156      #address-cells = <1>;
157      #size-cells = <1>;
158      ranges;
159
160      gpio0: gpio@20034000 {
161        compatible = "rockchip,gpio-bank";
162        reg = <0x20034000 0x100>;
163        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
164        clocks = <&clk_gates8 9>;
165
166        gpio-controller;
167        #gpio-cells = <2>;
168
169        interrupt-controller;
170        #interrupt-cells = <2>;
171      };
172
173      pcfg_pull_default: pcfg-pull-default {
174        bias-pull-pin-default;
175      };
176
177      uart2 {
178        uart2_xfer: uart2-xfer {
179          rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
180                          <1 RK_PB1 1 &pcfg_pull_default>;
181        };
182      };
183    };
184
185    uart2: serial@20064000 {
186      compatible = "snps,dw-apb-uart";
187      reg = <0x20064000 0x400>;
188      interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
189      clocks = <&mux_uart2>;
190      pinctrl-0 = <&uart2_xfer>;
191      pinctrl-names = "default";
192      reg-io-width = <1>;
193      reg-shift = <2>;
194    };