renesas,rzg2l-pinctrl.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller
  8
  9maintainers:
 10  - Geert Uytterhoeven <geert+renesas@glider.be>
 11  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
 12
 13description:
 14  The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and
 15  GPIO controller.
 16  Pin multiplexing and GPIO configuration is performed on a per-pin basis.
 17  Each port features up to 8 pins, each of them configurable for GPIO function
 18  (port mode) or in alternate function mode.
 19  Up to 8 different alternate function modes exist for each single pin.
 20
 21properties:
 22  compatible:
 23    oneOf:
 24      - items:
 25          - enum:
 26              - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
 27              - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
 28              - renesas,r9a08g045-pinctrl # RZ/G3S
 29              - renesas,r9a09g047-pinctrl # RZ/G3E
 30              - renesas,r9a09g056-pinctrl # RZ/V2N
 31              - renesas,r9a09g057-pinctrl # RZ/V2H(P)
 32
 33      - items:
 34          - enum:
 35              - renesas,r9a07g054-pinctrl     # RZ/V2L
 36          - const: renesas,r9a07g044-pinctrl  # RZ/G2{L,LC} fallback for RZ/V2L
 37
 38  reg:
 39    maxItems: 1
 40
 41  gpio-controller: true
 42
 43  '#gpio-cells':
 44    const: 2
 45    description:
 46      The first cell contains the global GPIO port index, constructed using the
 47      RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
 48      second cell represents consumer flag as mentioned in ../gpio/gpio.txt
 49      E.g. "RZG2L_GPIO(39, 1)" for P39_1.
 50
 51  gpio-ranges:
 52    maxItems: 1
 53
 54  interrupt-controller: true
 55
 56  '#interrupt-cells':
 57    const: 2
 58    description:
 59      The first cell contains the global GPIO port index, constructed using the
 60      RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
 61      second cell is used to specify the flag.
 62      E.g. "interrupts = <RZG2L_GPIO(43, 0) IRQ_TYPE_EDGE_FALLING>;" if P43_0 is
 63      being used as an interrupt.
 64
 65  clocks:
 66    maxItems: 1
 67
 68  power-domains:
 69    maxItems: 1
 70
 71  resets:
 72    oneOf:
 73      - items:
 74          - description: GPIO_RSTN signal
 75          - description: GPIO_PORT_RESETN signal
 76          - description: GPIO_SPARE_RESETN signal
 77      - items:
 78          - description: PFC main reset
 79          - description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins
 80
 81additionalProperties:
 82  anyOf:
 83    - type: object
 84      additionalProperties: false
 85      allOf:
 86        - $ref: pincfg-node.yaml#
 87        - $ref: pinmux-node.yaml#
 88
 89      description:
 90        Pin controller client devices use pin configuration subnodes (children
 91        and grandchildren) for desired pin configuration.
 92        Client device subnodes use below standard properties.
 93
 94      properties:
 95        pinmux:
 96          description:
 97            Values are constructed from GPIO port number, pin number, and
 98            alternate function configuration number using the RZG2L_PORT_PINMUX()
 99            helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>.
100        pins: true
101        drive-strength:
102          enum: [ 2, 4, 8, 12 ]
103        drive-strength-microamp:
104          enum: [ 1900, 2200, 4000, 4400, 4500, 4700, 5200, 5300, 5700,
105                  5800, 6000, 6050, 6100, 6550, 6800, 7000, 8000, 9000,
106                  10000 ]
107        output-impedance-ohms:
108          enum: [ 33, 50, 66, 100 ]
109        power-source:
110          description: I/O voltage in millivolt.
111          enum: [ 1800, 2500, 3300 ]
112        slew-rate: true
113        gpio-hog: true
114        gpios: true
115        input: true
116        input-enable: true
117        output-enable: true
118        output-high: true
119        output-low: true
120        line-name: true
121        bias-disable: true
122        bias-pull-down: true
123        bias-pull-up: true
124        input-schmitt-enable: true
125        input-schmitt-disable: true
126        drive-open-drain: true
127        drive-push-pull: true
128        renesas,output-impedance:
129          description:
130            Output impedance for pins on the RZ/{G3E,V2H(P)} SoC. The value provided by this
131            property corresponds to register bit values that can be set in the PFC_IOLH_mn
132            register, which adjusts the drive strength value and is pin-dependent.
133          $ref: /schemas/types.yaml#/definitions/uint32
134          enum: [0, 1, 2, 3]
135
136    - type: object
137      additionalProperties:
138        $ref: '#/additionalProperties/anyOf/0'
139
140allOf:
141  - $ref: pinctrl.yaml#
142
143  - if:
144      properties:
145        compatible:
146          contains:
147            enum:
148              - renesas,r9a09g047-pinctrl
149              - renesas,r9a09g056-pinctrl
150              - renesas,r9a09g057-pinctrl
151    then:
152      properties:
153        resets:
154          maxItems: 2
155    else:
156      properties:
157        resets:
158          minItems: 3
159
160required:
161  - compatible
162  - reg
163  - gpio-controller
164  - '#gpio-cells'
165  - gpio-ranges
166  - interrupt-controller
167  - '#interrupt-cells'
168  - clocks
169  - power-domains
170  - resets
171
172examples:
173  - |
174    #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
175    #include <dt-bindings/clock/r9a07g044-cpg.h>
176
177    pinctrl: pinctrl@11030000 {
178            compatible = "renesas,r9a07g044-pinctrl";
179            reg = <0x11030000 0x10000>;
180
181            gpio-controller;
182            #gpio-cells = <2>;
183            gpio-ranges = <&pinctrl 0 0 392>;
184            interrupt-controller;
185            #interrupt-cells = <2>;
186            clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
187            resets = <&cpg R9A07G044_GPIO_RSTN>,
188                     <&cpg R9A07G044_GPIO_PORT_RESETN>,
189                     <&cpg R9A07G044_GPIO_SPARE_RESETN>;
190            power-domains = <&cpg>;
191
192            scif0_pins: serial0 {
193                    pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */
194                             <RZG2L_PORT_PINMUX(38, 1, 1)>; /* Rx */
195            };
196
197            i2c1_pins: i2c1 {
198                    pins = "RIIC1_SDA", "RIIC1_SCL";
199                    input-enable;
200            };
201
202            sd1-pwr-en-hog {
203                    gpio-hog;
204                    gpios = <RZG2L_GPIO(39, 2) 0>;
205                    output-high;
206                    line-name = "sd1_pwr_en";
207            };
208
209            sdhi1_pins: sd1 {
210                    sd1_mux {
211                            pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */
212                                     <RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */
213                            power-source = <3300>;
214                    };
215
216                    sd1_data {
217                            pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
218                            power-source = <3300>;
219                    };
220
221                    sd1_ctrl {
222                            pins = "SD1_CLK", "SD1_CMD";
223                            power-source = <3300>;
224                    };
225            };
226    };