renesas,pfc.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pinctrl/renesas,pfc.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Renesas Pin Function Controller (GPIO and Pin Mux/Config)
  8
  9maintainers:
 10  - Geert Uytterhoeven <geert+renesas@glider.be>
 11
 12description:
 13  The Pin Function Controller (PFC) is a Pin Mux/Config controller.
 14  On SH/R-Mobile SoCs it also acts as a GPIO controller.
 15
 16properties:
 17  compatible:
 18    enum:
 19      - renesas,pfc-emev2       # EMMA Mobile EV2
 20      - renesas,pfc-r8a73a4     # R-Mobile APE6
 21      - renesas,pfc-r8a7740     # R-Mobile A1
 22      - renesas,pfc-r8a7742     # RZ/G1H
 23      - renesas,pfc-r8a7743     # RZ/G1M
 24      - renesas,pfc-r8a7744     # RZ/G1N
 25      - renesas,pfc-r8a7745     # RZ/G1E
 26      - renesas,pfc-r8a77470    # RZ/G1C
 27      - renesas,pfc-r8a774a1    # RZ/G2M
 28      - renesas,pfc-r8a774a3    # RZ/G2M v3.0
 29      - renesas,pfc-r8a774b1    # RZ/G2N
 30      - renesas,pfc-r8a774c0    # RZ/G2E
 31      - renesas,pfc-r8a774e1    # RZ/G2H
 32      - renesas,pfc-r8a7778     # R-Car M1
 33      - renesas,pfc-r8a7779     # R-Car H1
 34      - renesas,pfc-r8a7790     # R-Car H2
 35      - renesas,pfc-r8a7791     # R-Car M2-W
 36      - renesas,pfc-r8a7792     # R-Car V2H
 37      - renesas,pfc-r8a7793     # R-Car M2-N
 38      - renesas,pfc-r8a7794     # R-Car E2
 39      - renesas,pfc-r8a7795     # R-Car H3
 40      - renesas,pfc-r8a7796     # R-Car M3-W
 41      - renesas,pfc-r8a77961    # R-Car M3-W+
 42      - renesas,pfc-r8a77965    # R-Car M3-N
 43      - renesas,pfc-r8a77970    # R-Car V3M
 44      - renesas,pfc-r8a77980    # R-Car V3H
 45      - renesas,pfc-r8a77990    # R-Car E3
 46      - renesas,pfc-r8a77995    # R-Car D3
 47      - renesas,pfc-r8a779a0    # R-Car V3U
 48      - renesas,pfc-r8a779f0    # R-Car S4-8
 49      - renesas,pfc-r8a779g0    # R-Car V4H
 50      - renesas,pfc-r8a779h0    # R-Car V4M
 51      - renesas,pfc-sh73a0      # SH-Mobile AG5
 52
 53  reg:
 54    minItems: 1
 55    maxItems: 10
 56
 57  gpio-controller: true
 58
 59  '#gpio-cells':
 60    const: 2
 61
 62  gpio-ranges:
 63    minItems: 1
 64    maxItems: 16
 65
 66  interrupts-extended:
 67    minItems: 32
 68    maxItems: 64
 69    description:
 70      Specify the interrupts associated with external IRQ pins on SoCs where
 71      the PFC acts as a GPIO controller.  It must contain one interrupt per
 72      external IRQ, sorted by external IRQ number.
 73
 74  power-domains:
 75    maxItems: 1
 76
 77allOf:
 78  - $ref: pinctrl.yaml#
 79
 80required:
 81  - compatible
 82  - reg
 83
 84if:
 85  properties:
 86    compatible:
 87      enum:
 88        - renesas,pfc-r8a73a4
 89        - renesas,pfc-r8a7740
 90        - renesas,pfc-sh73a0
 91then:
 92  required:
 93    - interrupts-extended
 94    - gpio-controller
 95    - '#gpio-cells'
 96    - gpio-ranges
 97    - power-domains
 98
 99additionalProperties:
100  anyOf:
101    - type: object
102      allOf:
103        - $ref: pincfg-node.yaml#
104        - $ref: pinmux-node.yaml#
105
106      description:
107        Pin controller client devices use pin configuration subnodes (children
108        and grandchildren) for desired pin configuration.
109        Client device subnodes use below standard properties.
110
111      properties:
112        function: true
113        groups: true
114        pins: true
115        bias-disable: true
116        bias-pull-down: true
117        bias-pull-up: true
118        drive-strength:
119          enum: [ 3, 6, 9, 12, 15, 18, 21, 24 ] # Superset of supported values
120        power-source:
121          enum: [ 1800, 3300 ]
122        gpio-hog: true
123        gpios: true
124        input: true
125        output-high: true
126        output-low: true
127
128      additionalProperties: false
129
130    - type: object
131      additionalProperties:
132        $ref: '#/additionalProperties/anyOf/0'
133
134examples:
135  - |
136    pfc: pinctrl@e6050000 {
137            compatible = "renesas,pfc-r8a7740";
138            reg = <0xe6050000 0x8000>,
139                  <0xe605800c 0x20>;
140            gpio-controller;
141            #gpio-cells = <2>;
142            gpio-ranges = <&pfc 0 0 212>;
143            interrupts-extended =
144                <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
145                <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
146                <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
147                <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
148                <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
149                <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
150                <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
151                <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
152            power-domains = <&pd_c5>;
153
154            lcd0-mux-hog {
155                    /* DBGMD/LCDC0/FSIA MUX */
156                    gpio-hog;
157                    gpios = <176 0>;
158                    output-high;
159            };
160    };
161
162  - |
163    pinctrl@e6060000 {
164            compatible = "renesas,pfc-r8a7795";
165            reg = <0xe6060000 0x50c>;
166
167            avb_pins: avb {
168                    mux {
169                            groups = "avb_link", "avb_mdio", "avb_mii";
170                            function = "avb";
171                    };
172
173                    pins_mdio {
174                            groups = "avb_mdio";
175                            drive-strength = <24>;
176                    };
177
178                    pins_mii_tx {
179                            pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC",
180                                   "PIN_AVB_TD0", "PIN_AVB_TD1", "PIN_AVB_TD2",
181                                   "PIN_AVB_TD3";
182                            drive-strength = <12>;
183                    };
184            };
185
186            keys_pins: keys {
187                    pins = "GP_5_17", "GP_5_20", "GP_5_22", "GP_2_1";
188                    bias-pull-up;
189            };
190
191            sdhi0_pins: sd0 {
192                    groups = "sdhi0_data4", "sdhi0_ctrl";
193                    function = "sdhi0";
194                    power-source = <3300>;
195            };
196    };