qcom,sm8750-tlmm.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8750-tlmm.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm Technologies, Inc. SM8750 TLMM block
  8
  9maintainers:
 10  - Melody Olvera <quic_molvera@quicinc.com>
 11
 12description:
 13  Top Level Mode Multiplexer pin controller in Qualcomm SM8750 SoC.
 14
 15allOf:
 16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
 17
 18properties:
 19  compatible:
 20    const: qcom,sm8750-tlmm
 21
 22  reg:
 23    maxItems: 1
 24
 25  interrupts:
 26    maxItems: 1
 27
 28  gpio-reserved-ranges:
 29    minItems: 1
 30    maxItems: 108
 31
 32  gpio-line-names:
 33    maxItems: 215
 34
 35patternProperties:
 36  "-state$":
 37    oneOf:
 38      - $ref: "#/$defs/qcom-sm8750-tlmm-state"
 39      - patternProperties:
 40          "-pins$":
 41            $ref: "#/$defs/qcom-sm8750-tlmm-state"
 42        additionalProperties: false
 43
 44$defs:
 45  qcom-sm8750-tlmm-state:
 46    type: object
 47    description:
 48      Pinctrl node's client devices use subnodes for desired pin configuration.
 49      Client device subnodes use below standard properties.
 50    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
 51    unevaluatedProperties: false
 52
 53    properties:
 54      pins:
 55        description:
 56          List of gpio pins affected by the properties specified in this
 57          subnode.
 58        items:
 59          oneOf:
 60            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-4])$"
 61            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
 62        minItems: 1
 63        maxItems: 36
 64
 65      function:
 66        description:
 67          Specify the alternative function to be configured for the specified
 68          pins.
 69        enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0,
 70                audio_ext_mclk1, audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4,
 71                cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer,
 72                cmu_rng, coex_uart1_rx, coex_uart1_tx, coex_uart2_rx,
 73                coex_uart2_tx, dbg_out_clk, ddr_bist_complete, ddr_bist_fail,
 74                ddr_bist_start, ddr_bist_stop, ddr_pxi0, ddr_pxi1, ddr_pxi2,
 75                ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2, gcc_gp3, gnss_adc0,
 76                gnss_adc1, i2chub0_se0, i2chub0_se1, i2chub0_se2, i2chub0_se3,
 77                i2chub0_se4, i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8,
 78                i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws,
 79                i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c, jitter_bist,
 80                mdp_esync0_out, mdp_esync1_out, mdp_vsync, mdp_vsync0_out,
 81                mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out,
 82                mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3,
 83                pcie0_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux,
 84                prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
 85                qlink_big_enable, qlink_big_request, qlink_little_enable,
 86                qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qspi3,
 87                qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3,
 88                qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1,
 89                qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, qup2_se7,
 90                sd_write_protect, sdc40, sdc41, sdc42, sdc43, sdc4_clk,
 91                sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4, tmess_prng0, tmess_prng1,
 92                tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3,
 93                tsense_pwm4, uim0_clk, uim0_data, uim0_present, uim0_reset,
 94                uim1_clk, uim1_data, uim1_present, uim1_reset, usb1_hs, usb_phy,
 95                vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ]
 96
 97    required:
 98      - pins
 99
100required:
101  - compatible
102  - reg
103
104unevaluatedProperties: false
105
106examples:
107  - |
108    #include <dt-bindings/interrupt-controller/arm-gic.h>
109    tlmm: pinctrl@f100000 {
110        compatible = "qcom,sm8750-tlmm";
111        reg = <0x0f100000 0x300000>;
112        gpio-controller;
113        #gpio-cells = <2>;
114        gpio-ranges = <&tlmm 0 0 216>;
115        interrupt-controller;
116        #interrupt-cells = <2>;
117        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
118
119        gpio-wo-state {
120            pins = "gpio1";
121            function = "gpio";
122        };
123
124        uart-w-state {
125            rx-pins {
126                pins = "gpio60";
127                function = "qup1_se7";
128                bias-pull-up;
129            };
130
131            tx-pins {
132                pins = "gpio61";
133                function = "qup1_se7";
134                bias-disable;
135            };
136        };
137    };
138...