qcom,sc8280xp-tlmm.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-tlmm.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm Technologies, Inc. SC8280XP TLMM block
  8
  9maintainers:
 10  - Bjorn Andersson <bjorn.andersson@linaro.org>
 11
 12description: |
 13  Top Level Mode Multiplexer pin controller in Qualcomm SC8280XP SoC.
 14
 15allOf:
 16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
 17
 18properties:
 19  compatible:
 20    const: qcom,sc8280xp-tlmm
 21
 22  reg:
 23    maxItems: 1
 24
 25  interrupts:
 26    maxItems: 1
 27
 28  gpio-reserved-ranges: true
 29
 30patternProperties:
 31  "-state$":
 32    oneOf:
 33      - $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
 34      - patternProperties:
 35          "-pins$":
 36            $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
 37        additionalProperties: false
 38
 39$defs:
 40  qcom-sc8280xp-tlmm-state:
 41    type: object
 42    description:
 43      Pinctrl node's client devices use subnodes for desired pin configuration.
 44      Client device subnodes use below standard properties.
 45    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
 46    unevaluatedProperties: false
 47
 48    properties:
 49      pins:
 50        description:
 51          List of gpio pins affected by the properties specified in this
 52          subnode.
 53        items:
 54          oneOf:
 55            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$"
 56            - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset, ufs1_reset ]
 57        minItems: 1
 58        maxItems: 16
 59
 60      function:
 61        description:
 62          Specify the alternative function to be configured for the specified
 63          pins.
 64
 65        enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, cci_i2c,
 66                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
 67                cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9,
 68                cmu_rng, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
 69                ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5,
 70                ddr_pxi6, ddr_pxi7, dp2_hot, dp3_hot, edp0_lcd, edp1_lcd,
 71                edp2_lcd, edp3_lcd, edp_hot, emac0_dll, emac0_mcg0, emac0_mcg1,
 72                emac0_mcg2, emac0_mcg3, emac0_phy, emac0_ptp, emac1_dll0,
 73                emac1_dll1, emac1_mcg0, emac1_mcg1, emac1_mcg2, emac1_mcg3,
 74                emac1_phy, emac1_ptp, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4,
 75                gcc_gp5, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s, ibi_i3c,
 76                jitter_bist, lpass_slimbus, mdp0_vsync0, mdp0_vsync1,
 77                mdp0_vsync2, mdp0_vsync3, mdp0_vsync4, mdp0_vsync5,
 78                mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, mdp1_vsync0,
 79                mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4,
 80                mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync,
 81                mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s1_data0,
 82                mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, mi2s2_data1,
 83                mi2s2_sck, mi2s2_ws, mi2s_mclk1, mi2s_mclk2, pcie2a_clkreq,
 84                pcie2b_clkreq, pcie3a_clkreq, pcie3b_clkreq, pcie4_clkreq,
 85                phase_flag, pll_bist, pll_clk, prng_rosc0, prng_rosc1,
 86                prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qspi, qspi_clk,
 87                qspi_cs, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
 88                qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
 89                qup18, qup19, qup20, qup21, qup22, qup23, rgmii_0, rgmii_1,
 90                sd_write, sdc40, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig,
 91                tgu, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
 92                usb0_dp, usb0_phy, usb0_sbrx, usb0_sbtx, usb0_usb4, usb1_dp,
 93                usb1_phy, usb1_sbrx, usb1_sbtx, usb1_usb4, usb2phy_ac,
 94                vsense_trigger ]
 95
 96    required:
 97      - pins
 98
 99required:
100  - compatible
101  - reg
102
103unevaluatedProperties: false
104
105examples:
106  - |
107    #include <dt-bindings/interrupt-controller/arm-gic.h>
108    pinctrl@f100000 {
109        compatible = "qcom,sc8280xp-tlmm";
110        reg = <0x0f100000 0x300000>;
111        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
112        gpio-controller;
113        #gpio-cells = <2>;
114        interrupt-controller;
115        #interrupt-cells = <2>;
116        gpio-ranges = <&tlmm 0 0 230>;
117
118        gpio-wo-subnode-state {
119            pins = "gpio1";
120            function = "gpio";
121        };
122
123        uart-w-subnodes-state {
124            rx-pins {
125                pins = "gpio4";
126                function = "qup14";
127                bias-pull-up;
128            };
129
130            tx-pins {
131                pins = "gpio5";
132                function = "qup14";
133                bias-disable;
134            };
135        };
136    };
137...