qcom,sc7180-pinctrl.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pinctrl/qcom,sc7180-pinctrl.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm SC7180 TLMM pin controller
  8
  9maintainers:
 10  - Bjorn Andersson <andersson@kernel.org>
 11  - Krzysztof Kozlowski <krzk@kernel.org>
 12
 13description:
 14  Top Level Mode Multiplexer pin controller in Qualcomm SC7180 SoC.
 15
 16properties:
 17  compatible:
 18    const: qcom,sc7180-pinctrl
 19
 20  reg:
 21    maxItems: 3
 22
 23  reg-names:
 24    items:
 25      - const: west
 26      - const: north
 27      - const: south
 28
 29  interrupts:
 30    maxItems: 1
 31
 32  gpio-reserved-ranges:
 33    minItems: 1
 34    maxItems: 60
 35
 36  gpio-line-names:
 37    maxItems: 119
 38
 39patternProperties:
 40  "-state$":
 41    oneOf:
 42      - $ref: "#/$defs/qcom-sc7180-tlmm-state"
 43      - patternProperties:
 44          "-pins$":
 45            $ref: "#/$defs/qcom-sc7180-tlmm-state"
 46        additionalProperties: false
 47
 48$defs:
 49  qcom-sc7180-tlmm-state:
 50    type: object
 51    description:
 52      Pinctrl node's client devices use subnodes for desired pin configuration.
 53      Client device subnodes use below standard properties.
 54    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
 55    unevaluatedProperties: false
 56
 57    properties:
 58      pins:
 59        description:
 60          List of gpio pins affected by the properties specified in this
 61          subnode.
 62        items:
 63          oneOf:
 64            - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
 65            - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
 66                      sdc2_cmd, sdc2_data, ufs_reset ]
 67        minItems: 1
 68        maxItems: 36
 69
 70      function:
 71        description:
 72          Specify the alternative function to be configured for the specified
 73          pins.
 74
 75        enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_char0,
 76                atest_char1, atest_char2, atest_char3, atest_tsens,
 77                atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
 78                atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21,
 79                atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk,
 80                cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2,
 81                cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0,
 82                ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, gcc_gp1,
 83                gcc_gp2, gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gps_tx,
 84                jitter_bist, ldo_en, ldo_update, lpass_ext, mdp_vsync,
 85                mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1,
 86                mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag, PLL_BIST,
 87                pll_bypassnl, pll_reset, prng_rosc, qdss, qdss_cti,
 88                qlink_enable, qlink_request, qspi_clk, qspi_cs, qspi_data,
 89                qup00, qup01, qup02_i2c, qup02_uart, qup03, qup04_i2c,
 90                qup04_uart, qup05, qup10, qup11_i2c, qup11_uart, qup12,
 91                qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb, sdc2_tb,
 92                sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
 93                tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt, usb_phy, vfr_1,
 94                _V_GPIO, _V_PPS_IN, _V_PPS_OUT, vsense_trigger, wlan1_adc0,
 95                wlan1_adc1, wlan2_adc0, wlan2_adc1 ]
 96
 97    required:
 98      - pins
 99
100allOf:
101  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
102
103required:
104  - compatible
105  - reg
106  - reg-names
107
108unevaluatedProperties: false
109
110examples:
111  - |
112    #include <dt-bindings/interrupt-controller/arm-gic.h>
113
114    tlmm: pinctrl@3500000 {
115        compatible = "qcom,sc7180-pinctrl";
116        reg = <0x03500000 0x300000>,
117              <0x03900000 0x300000>,
118              <0x03d00000 0x300000>;
119        reg-names = "west", "north", "south";
120        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
121        gpio-controller;
122        #gpio-cells = <2>;
123        interrupt-controller;
124        #interrupt-cells = <2>;
125        gpio-ranges = <&tlmm 0 0 120>;
126        wakeup-parent = <&pdc>;
127
128        dp_hot_plug_det: dp-hot-plug-det-state {
129            pins = "gpio117";
130            function = "dp_hot";
131        };
132
133        qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
134            spi-pins {
135                pins = "gpio53", "gpio54", "gpio55";
136                function = "qup15";
137            };
138
139            cs-pins {
140                pins = "gpio56";
141                function = "gpio";
142            };
143        };
144    };