qcom,qdu1000-tlmm.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pinctrl/qcom,qdu1000-tlmm.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm Technologies, Inc. QDU1000/QRU1000 TLMM block
  8
  9maintainers:
 10  - Melody Olvera <quic_molvera@quicinc.com>
 11
 12description: |
 13  Top Level Mode Multiplexer pin controller found in the QDU1000 and
 14  QRU1000 SoCs.
 15
 16allOf:
 17  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
 18
 19properties:
 20  compatible:
 21    const: qcom,qdu1000-tlmm
 22
 23  reg:
 24    maxItems: 1
 25
 26  interrupts:
 27    maxItems: 1
 28
 29  gpio-reserved-ranges:
 30    minItems: 1
 31    maxItems: 76
 32
 33  gpio-line-names:
 34    maxItems: 151
 35
 36patternProperties:
 37  "-state$":
 38    oneOf:
 39      - $ref: "#/$defs/qcom-qdu1000-tlmm-state"
 40      - patternProperties:
 41          "-pins$":
 42            $ref: "#/$defs/qcom-qdu1000-tlmm-state"
 43        additionalProperties: false
 44
 45$defs:
 46  qcom-qdu1000-tlmm-state:
 47    type: object
 48    description:
 49      Pinctrl node's client devices use subnodes for desired pin configuration.
 50      Client device subnodes use below standard properties.
 51    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
 52    unevaluatedProperties: false
 53
 54    properties:
 55      pins:
 56        description:
 57          List of gpio pins affected by the properties specified in this
 58          subnode.
 59        items:
 60          oneOf:
 61            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|150)$"
 62            - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data ]
 63        minItems: 1
 64        maxItems: 36
 65
 66      function:
 67        description:
 68          Specify the alternative function to be configured for the specified
 69          pins.
 70        enum: [ atest_char, atest_usb, char_exec, CMO_PRI, cmu_rng,
 71                dbg_out_clk, ddr_bist, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4,
 72                ddr_pxi5, ddr_pxi6, ddr_pxi7, eth012_int_n, eth345_int_n,
 73                gcc_gp1, gcc_gp2, gcc_gp3, gpio, gps_pps_in, hardsync_pps_in,
 74                intr_c, jitter_bist_ref, pcie_clkreqn, phase_flag, pll_bist,
 75                pll_clk, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable,
 76                qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
 77                qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss,
 78                qlink3_enable, qlink3_request, qlink3_wmss, qlink4_enable,
 79                qlink4_request, qlink4_wmss, qlink5_enable, qlink5_request,
 80                qlink5_wmss, qlink6_enable, qlink6_request, qlink6_wmss,
 81                qlink7_enable, qlink7_request, qlink7_wmss, qspi_clk, qspi_cs,
 82                qspi0, qspi1, qspi2, qspi3, qup00, qup01, qup02, qup03, qup04,
 83                qup05, qup06, qup07, qup08, qup10, qup11, qup12, qup13, qup14,
 84                qup15, qup16, qup17, qup20, qup21, qup22, SI5518_INT, smb_alert,
 85                smb_clk, smb_dat, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
 86                tgu_ch4, tgu_ch5, tgu_ch6, tgu_ch7, tmess_prng0, tmess_prng1,
 87                tmess_prng2, tmess_prng3, tod_pps_in, tsense_pwm1, tsense_pwm2,
 88                usb2phy_ac, usb_con_det, usb_dfp_en, usb_phy, vfr_0, vfr_1,
 89                vsense_trigger ]
 90
 91    required:
 92      - pins
 93
 94required:
 95  - compatible
 96  - reg
 97
 98unevaluatedProperties: false
 99
100examples:
101  - |
102    #include <dt-bindings/interrupt-controller/arm-gic.h>
103
104    pinctrl@f000000 {
105        compatible = "qcom,qdu1000-tlmm";
106        reg = <0xf000000 0x1000000>;
107        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
108        gpio-controller;
109        #gpio-cells = <2>;
110        interrupt-controller;
111        #interrupt-cells = <2>;
112        gpio-ranges = <&tlmm 0 0 151>;
113        wakeup-parent = <&pdc>;
114
115        uart0-default-state {
116            pins = "gpio6", "gpio7", "gpio8", "gpio9";
117            function = "qup00";
118        };
119    };