qcom,msm8994-pinctrl.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pinctrl/qcom,msm8994-pinctrl.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm MSM8994 TLMM pin controller
  8
  9maintainers:
 10  - Bjorn Andersson <andersson@kernel.org>
 11  - Krzysztof Kozlowski <krzk@kernel.org>
 12
 13description:
 14  Top Level Mode Multiplexer pin controller in Qualcomm MSM8994 SoC.
 15
 16properties:
 17  compatible:
 18    enum:
 19      - qcom,msm8992-pinctrl
 20      - qcom,msm8994-pinctrl
 21
 22  reg:
 23    maxItems: 1
 24
 25  interrupts:
 26    maxItems: 1
 27
 28  gpio-reserved-ranges:
 29    minItems: 1
 30    maxItems: 73
 31
 32  gpio-line-names:
 33    maxItems: 146
 34
 35patternProperties:
 36  "-state$":
 37    oneOf:
 38      - $ref: "#/$defs/qcom-msm8994-tlmm-state"
 39      - patternProperties:
 40          "-pins$":
 41            $ref: "#/$defs/qcom-msm8994-tlmm-state"
 42        additionalProperties: false
 43
 44$defs:
 45  qcom-msm8994-tlmm-state:
 46    type: object
 47    description:
 48      Pinctrl node's client devices use subnodes for desired pin configuration.
 49      Client device subnodes use below standard properties.
 50    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
 51    unevaluatedProperties: false
 52
 53    properties:
 54      pins:
 55        description:
 56          List of gpio pins affected by the properties specified in this
 57          subnode.
 58        items:
 59          oneOf:
 60            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-5])$"
 61            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
 62                      sdc2_cmd, sdc2_data, sdc3_clk, sdc3_cmd, sdc3_data ]
 63        minItems: 1
 64        maxItems: 36
 65
 66      function:
 67        description:
 68          Specify the alternative function to be configured for the specified
 69          pins.
 70
 71        enum: [ gpio, audio_ref_clk, blsp_i2c1, blsp_i2c2, blsp_i2c3,
 72                blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
 73                blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, blsp_spi1,
 74                blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3, blsp_spi2,
 75                blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3,
 76                blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8,
 77                blsp_spi9, blsp_spi10, blsp_spi10_cs1, blsp_spi10_cs2,
 78                blsp_spi10_cs3, blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2,
 79                blsp_uart3, blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7,
 80                blsp_uart8, blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12,
 81                blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
 82                blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10,
 83                blsp_uim11, blsp_uim12, blsp11_i2c_scl_b, blsp11_i2c_sda_b,
 84                blsp11_uart_rx_b, blsp11_uart_tx_b, cam_mclk0, cam_mclk1,
 85                cam_mclk2, cam_mclk3, cci_async_in0, cci_async_in1,
 86                cci_async_in2, cci_i2c0, cci_i2c1, cci_timer0, cci_timer1,
 87                cci_timer2, cci_timer3, cci_timer4, gcc_gp1_clk_a,
 88                gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a,
 89                gcc_gp3_clk_b, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk,
 90                gp1_clk, gps_tx, gsm_tx, hdmi_cec, hdmi_ddc, hdmi_hpd,
 91                hdmi_rcv, mdp_vsync, mss_lte, nav_pps, nav_tsync,
 92                qdss_cti_trig_in_a, qdss_cti_trig_in_b, qdss_cti_trig_in_c,
 93                qdss_cti_trig_in_d, qdss_cti_trig_out_a, qdss_cti_trig_out_b,
 94                qdss_cti_trig_out_c, qdss_cti_trig_out_d, qdss_traceclk_a,
 95                qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
 96                qdss_tracedata_a, qdss_tracedata_b, qua_mi2s, pci_e0, pci_e1,
 97                pri_mi2s, sdc4, sec_mi2s, slimbus, spkr_i2s, ter_mi2s, tsif1,
 98                tsif2, uim_batt_alarm, uim1, uim2, uim3, uim4 ]
 99
100    required:
101      - pins
102
103allOf:
104  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
105
106required:
107  - compatible
108  - reg
109
110unevaluatedProperties: false
111
112examples:
113  - |
114    #include <dt-bindings/interrupt-controller/arm-gic.h>
115
116    tlmm: pinctrl@fd510000 {
117        compatible = "qcom,msm8994-pinctrl";
118        reg = <0xfd510000 0x4000>;
119        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
120        gpio-controller;
121        gpio-ranges = <&tlmm 0 0 146>;
122        #gpio-cells = <2>;
123        interrupt-controller;
124        #interrupt-cells = <2>;
125
126        blsp1-uart2-default-state {
127            function = "blsp_uart2";
128            pins = "gpio4", "gpio5";
129            drive-strength = <16>;
130            bias-disable;
131        };
132
133        blsp1-spi1-default-state {
134            default-pins {
135                pins = "gpio0", "gpio1", "gpio3";
136                function = "blsp_spi1";
137                drive-strength = <10>;
138                bias-pull-down;
139            };
140
141            cs-pins {
142                pins = "gpio8";
143                function = "gpio";
144                drive-strength = <2>;
145                bias-disable;
146            };
147        };
148    };