qcom,msm8226-pinctrl.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pinctrl/qcom,msm8226-pinctrl.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm Technologies, Inc. MSM8226 TLMM block
  8
  9maintainers:
 10  - Bjorn Andersson <bjorn.andersson@linaro.org>
 11
 12description:
 13  Top Level Mode Multiplexer pin controller in Qualcomm MSM8226 SoC.
 14
 15properties:
 16  compatible:
 17    const: qcom,msm8226-pinctrl
 18
 19  reg:
 20    description: Specifies the base address and size of the TLMM register space
 21    maxItems: 1
 22
 23  interrupts:
 24    maxItems: 1
 25
 26  gpio-reserved-ranges:
 27    maxItems: 1
 28
 29patternProperties:
 30  "-state$":
 31    oneOf:
 32      - $ref: "#/$defs/qcom-msm8226-tlmm-state"
 33      - patternProperties:
 34          "-pins$":
 35            $ref: "#/$defs/qcom-msm8226-tlmm-state"
 36        additionalProperties: false
 37
 38$defs:
 39  qcom-msm8226-tlmm-state:
 40    type: object
 41    description:
 42      Pinctrl node's client devices use subnodes for desired pin configuration.
 43      Client device subnodes use below standard properties.
 44    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
 45    unevaluatedProperties: false
 46
 47    properties:
 48      pins:
 49        description:
 50          List of gpio pins affected by the properties specified in this
 51          subnode.
 52        items:
 53          oneOf:
 54            - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-6])$"
 55            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
 56        minItems: 1
 57        maxItems: 36
 58
 59      function:
 60        description:
 61          Specify the alternative function to be configured for the specified
 62          pins. Functions are only valid for gpio pins.
 63        enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5,
 64                blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_i2c6,
 65                blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2,
 66                blsp_uart3, blsp_uart4, blsp_uart5, cam_mclk0, cam_mclk1,
 67                gp0_clk, gp1_clk, sdc3, wlan ]
 68
 69    required:
 70      - pins
 71
 72allOf:
 73  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
 74
 75required:
 76  - compatible
 77  - reg
 78
 79unevaluatedProperties: false
 80
 81examples:
 82  - |
 83    #include <dt-bindings/interrupt-controller/arm-gic.h>
 84    msmgpio: pinctrl@fd510000 {
 85        compatible = "qcom,msm8226-pinctrl";
 86        reg = <0xfd510000 0x4000>;
 87
 88        gpio-controller;
 89        #gpio-cells = <2>;
 90        gpio-ranges = <&msmgpio 0 0 117>;
 91        interrupt-controller;
 92        #interrupt-cells = <2>;
 93        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 94
 95        serial-state {
 96            pins = "gpio8", "gpio9";
 97            function = "blsp_uart3";
 98            drive-strength = <8>;
 99            bias-disable;
100        };
101    };