qcom,milos-tlmm.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pinctrl/qcom,milos-tlmm.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm Technologies, Inc. Milos TLMM block
  8
  9maintainers:
 10  - Luca Weiss <luca.weiss@fairphone.com>
 11
 12description:
 13  Top Level Mode Multiplexer pin controller in Qualcomm Milos SoC.
 14
 15allOf:
 16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
 17
 18properties:
 19  compatible:
 20    const: qcom,milos-tlmm
 21
 22  reg:
 23    maxItems: 1
 24
 25  interrupts:
 26    maxItems: 1
 27
 28  gpio-reserved-ranges:
 29    minItems: 1
 30    maxItems: 84
 31
 32  gpio-line-names:
 33    maxItems: 167
 34
 35patternProperties:
 36  "-state$":
 37    oneOf:
 38      - $ref: "#/$defs/qcom-milos-tlmm-state"
 39      - patternProperties:
 40          "-pins$":
 41            $ref: "#/$defs/qcom-milos-tlmm-state"
 42        additionalProperties: false
 43
 44$defs:
 45  qcom-milos-tlmm-state:
 46    type: object
 47    description:
 48      Pinctrl node's client devices use subnodes for desired pin configuration.
 49      Client device subnodes use below standard properties.
 50    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
 51    unevaluatedProperties: false
 52
 53    properties:
 54      pins:
 55        description:
 56          List of gpio pins affected by the properties specified in this
 57          subnode.
 58        items:
 59          oneOf:
 60            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-5][0-9]|16[0-7])$"
 61            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
 62        minItems: 1
 63        maxItems: 36
 64
 65      function:
 66        description:
 67          Specify the alternative function to be configured for the specified
 68          pins.
 69        enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0,
 70                audio_ext_mclk1, audio_ref_clk, cam_mclk, cci_async_in0,
 71                cci_i2c_scl, cci_i2c_sda, cci_timer, coex_uart1_rx,
 72                coex_uart1_tx, dbg_out_clk, ddr_bist_complete, ddr_bist_fail,
 73                ddr_bist_start, ddr_bist_stop, ddr_pxi0, ddr_pxi1, dp0_hot,
 74                egpio, gcc_gp1, gcc_gp2, gcc_gp3, host2wlan_sol, i2s0_data0,
 75                i2s0_data1, i2s0_sck, i2s0_ws, ibi_i3c, jitter_bist, mdp_vsync,
 76                mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out,
 77                mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, pcie0_clk_req_n,
 78                pcie1_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux,
 79                prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
 80                qdss_gpio, qlink0_enable, qlink0_request, qlink0_wmss,
 81                qlink1_enable, qlink1_request, qlink1_wmss, qspi0, qup0_se0,
 82                qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5, qup0_se6,
 83                qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5,
 84                qup1_se6, resout_gpio_n, sd_write_protect, sdc1_clk, sdc1_cmd,
 85                sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data,
 86                sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tgu_ch0_trigout,
 87                tgu_ch1_trigout, tmess_prng0, tmess_prng1, tmess_prng2,
 88                tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data,
 89                uim0_present, uim0_reset, uim1_clk_mira, uim1_clk_mirb,
 90                uim1_data_mira, uim1_data_mirb, uim1_present_mira,
 91                uim1_present_mirb, uim1_reset_mira, uim1_reset_mirb, usb0_hs,
 92                usb0_phy_ps, vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw,
 93                wcn_sw_ctrl ]
 94
 95    required:
 96      - pins
 97
 98required:
 99  - compatible
100  - reg
101
102unevaluatedProperties: false
103
104examples:
105  - |
106    #include <dt-bindings/interrupt-controller/arm-gic.h>
107    tlmm: pinctrl@f100000 {
108        compatible = "qcom,milos-tlmm";
109        reg = <0x0f100000 0x300000>;
110
111        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
112
113        gpio-controller;
114        #gpio-cells = <2>;
115
116        interrupt-controller;
117        #interrupt-cells = <2>;
118
119        gpio-ranges = <&tlmm 0 0 168>;
120
121        gpio-wo-state {
122            pins = "gpio1";
123            function = "gpio";
124        };
125
126        qup-uart5-default-state {
127            pins = "gpio25", "gpio26";
128            function = "qup0_se5";
129            drive-strength = <2>;
130            bias-disable;
131        };
132    };
133...