qcom,mdm9615-pinctrl.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pinctrl/qcom,mdm9615-pinctrl.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm Technologies, Inc. MDM9615 TLMM block
  8
  9maintainers:
 10  - Bjorn Andersson <andersson@kernel.org>
 11
 12description: Top Level Mode Multiplexer pin controller in Qualcomm MDM9615 SoC.
 13
 14$ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
 15
 16properties:
 17  compatible:
 18    const: qcom,mdm9615-pinctrl
 19
 20  reg:
 21    maxItems: 1
 22
 23  interrupts:
 24    maxItems: 1
 25
 26patternProperties:
 27  "-state$":
 28    oneOf:
 29      - $ref: "#/$defs/qcom-mdm9615-pinctrl-state"
 30      - patternProperties:
 31          "-pins$":
 32            $ref: "#/$defs/qcom-mdm9615-pinctrl-state"
 33        additionalProperties: false
 34
 35$defs:
 36  qcom-mdm9615-pinctrl-state:
 37    type: object
 38    description:
 39      Pinctrl node's client devices use subnodes for desired pin configuration.
 40      Client device subnodes use below standard properties.
 41    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
 42    unevaluatedProperties: false
 43
 44    properties:
 45      pins:
 46        description:
 47          List of gpio pins affected by the properties specified in this
 48          subnode.
 49        items:
 50          pattern: "^gpio([0-9]|[1-7][0-9]|8[0-7])$"
 51        minItems: 1
 52        maxItems: 16
 53
 54      function:
 55        description:
 56          Specify the alternative function to be configured for the specified
 57          pins.
 58
 59        enum: [ gpio, gsbi2_i2c, gsbi3, gsbi4, gsbi5_i2c, gsbi5_uart,
 60                sdc2, ebi2_lcdc, ps_hold, prim_audio, sec_audio, cdc_mclk, ]
 61
 62    required:
 63      - pins
 64
 65required:
 66  - compatible
 67  - reg
 68
 69unevaluatedProperties: false
 70
 71examples:
 72  - |
 73    #include <dt-bindings/interrupt-controller/arm-gic.h>
 74    tlmm: pinctrl@1000000 {
 75      compatible = "qcom,mdm9615-pinctrl";
 76      reg = <0x01000000 0x300000>;
 77      interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 78      gpio-controller;
 79      gpio-ranges = <&msmgpio 0 0 88>;
 80      #gpio-cells = <2>;
 81      interrupt-controller;
 82      #interrupt-cells = <2>;
 83
 84      gsbi3-state {
 85        pins = "gpio8", "gpio9", "gpio10", "gpio11";
 86        function = "gsbi3";
 87        drive-strength = <8>;
 88        bias-disable;
 89      };
 90
 91      gsbi5-i2c-state {
 92        sda-pins {
 93          pins = "gpio16";
 94          function = "gsbi5_i2c";
 95          drive-strength = <8>;
 96          bias-disable;
 97        };
 98
 99        scl-pins {
100          pins = "gpio17";
101          function = "gsbi5_i2c";
102          drive-strength = <2>;
103          bias-disable;
104        };
105      };
106    };