qcom,apq8064-pinctrl.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pinctrl/qcom,apq8064-pinctrl.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm Technologies, Inc. APQ8064 TLMM block
  8
  9maintainers:
 10  - Bjorn Andersson <bjorn.andersson@linaro.org>
 11
 12description: |
 13  Top Level Mode Multiplexer pin controller in Qualcomm APQ8064 SoC.
 14
 15allOf:
 16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
 17
 18properties:
 19  compatible:
 20    const: qcom,apq8064-pinctrl
 21
 22  reg:
 23    maxItems: 1
 24
 25  interrupts:
 26    maxItems: 1
 27
 28  gpio-reserved-ranges: true
 29
 30patternProperties:
 31  "-state$":
 32    oneOf:
 33      - $ref: "#/$defs/qcom-apq8064-tlmm-state"
 34      - patternProperties:
 35          "-pins$":
 36            $ref: "#/$defs/qcom-apq8064-tlmm-state"
 37        additionalProperties: false
 38
 39$defs:
 40  qcom-apq8064-tlmm-state:
 41    type: object
 42    description:
 43      Pinctrl node's client devices use subnodes for desired pin configuration.
 44      Client device subnodes use below standard properties.
 45    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
 46    unevaluatedProperties: false
 47
 48    properties:
 49      pins:
 50        description:
 51          List of gpio pins affected by the properties specified in this
 52          subnode.
 53        items:
 54          oneOf:
 55            - pattern: "^gpio([0-9]|[1-8][0-9])$"
 56            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc3_clk, sdc3_cmd, sdc3_data ]
 57        minItems: 1
 58        maxItems: 36
 59
 60      function:
 61        description:
 62          Specify the alternative function to be configured for the specified
 63          pins.
 64        enum: [ cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a,
 65                gp_clk_0b, gp_clk_1a, gp_clk_1b, gp_clk_2a, gp_clk_2b,
 66                gpio, gsbi1, gsbi2, gsbi3, gsbi4, gsbi4_cam_i2c,
 67                gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3,
 68                gsbi6, gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3,
 69                gsbi7, gsbi7_spi_cs1, gsbi7_spi_cs2, gsbi7_spi_cs3,
 70                gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm, riva_wlan,
 71                sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic,
 72                ps_hold ]
 73
 74    required:
 75      - pins
 76
 77required:
 78  - compatible
 79  - reg
 80
 81unevaluatedProperties: false
 82
 83examples:
 84  - |
 85    #include <dt-bindings/interrupt-controller/arm-gic.h>
 86    tlmm: pinctrl@800000 {
 87        compatible = "qcom,apq8064-pinctrl";
 88        reg = <0x800000 0x4000>;
 89
 90        gpio-controller;
 91        #gpio-cells = <2>;
 92        gpio-ranges = <&tlmm 0 0 90>;
 93        interrupt-controller;
 94        #interrupt-cells = <2>;
 95        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 96
 97        uart-state {
 98            rx-pins {
 99                pins = "gpio52";
100                function = "gsbi5";
101                bias-pull-up;
102            };
103
104            tx-pins {
105                pins = "gpio51";
106                function = "gsbi5";
107                bias-disable;
108            };
109        };
110    };