pinctrl-single.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Generic Pin Controller with a Single Register for One or More Pins
  8
  9maintainers:
 10  - Tony Lindgren <tony@atomide.com>
 11
 12description:
 13  Some pin controller devices use a single register for one or more pins. The
 14  range of pin control registers can vary from one to many for each controller
 15  instance. Some SoCs from Altera, Broadcom, HiSilicon, Ralink, and TI have this
 16  kind of pin controller instances.
 17
 18properties:
 19  compatible:
 20    oneOf:
 21      - enum:
 22          - pinctrl-single
 23          - pinconf-single
 24      - items:
 25          - enum:
 26              - ti,am437-padconf
 27              - ti,am62l-padconf
 28              - ti,am654-padconf
 29              - ti,dra7-padconf
 30              - ti,omap2420-padconf
 31              - ti,omap2430-padconf
 32              - ti,omap3-padconf
 33              - ti,omap4-padconf
 34              - ti,omap5-padconf
 35              - ti,j7200-padconf
 36          - const: pinctrl-single
 37      - items:
 38          - enum:
 39              - marvell,pxa1908-padconf
 40          - const: pinconf-single
 41
 42  reg:
 43    maxItems: 1
 44
 45  interrupt-controller: true
 46
 47  '#interrupt-cells':
 48    const: 1
 49
 50  '#address-cells':
 51    const: 1
 52
 53  '#size-cells':
 54    const: 0
 55
 56  '#pinctrl-cells':
 57    description:
 58      Number of cells. Usually 2, consisting of register offset, pin configuration
 59      value, and pinmux mode. Some controllers may use 1 for just offset and value.
 60    enum: [ 1, 2 ]
 61
 62  pinctrl-single,bit-per-mux:
 63    description: Optional flag to indicate register controls more than one pin
 64    type: boolean
 65
 66  pinctrl-single,function-mask:
 67    description: Mask of the allowed register bits
 68    $ref: /schemas/types.yaml#/definitions/uint32
 69
 70  pinctrl-single,function-off:
 71    description: Optional function off mode for disabled state
 72    $ref: /schemas/types.yaml#/definitions/uint32
 73
 74  pinctrl-single,register-width:
 75    description: Width of pin specific bits in the register
 76    $ref: /schemas/types.yaml#/definitions/uint32
 77    enum: [ 8, 16, 32 ]
 78
 79  pinctrl-single,gpio-range:
 80    description: Optional list of pin base, nr pins & gpio function
 81    $ref: /schemas/types.yaml#/definitions/phandle-array
 82    items:
 83      items:
 84        - description: phandle of a gpio-range node
 85        - description: pin base
 86        - description: number of pins
 87        - description: gpio function
 88
 89  '#gpio-range-cells':
 90    description: No longer needed, may exist in older files for gpio-ranges
 91    deprecated: true
 92    const: 3
 93
 94  gpio-range:
 95    description: Optional node for gpio range cells
 96    type: object
 97    additionalProperties: false
 98    properties:
 99      '#pinctrl-single,gpio-range-cells':
100        description: Number of gpio range cells
101        const: 3
102        $ref: /schemas/types.yaml#/definitions/uint32
103
104patternProperties:
105  '-pins(-[0-9]+)?$|-pin$':
106    description:
107      Pin group node name using naming ending in -pins followed by an optional
108      instance number
109    type: object
110    additionalProperties: false
111
112    properties:
113      pinctrl-single,pins:
114        description:
115          Array of pins as described in pinmux-node.yaml for pinctrl-pin-array
116        $ref: /schemas/types.yaml#/definitions/uint32-array
117
118      pinctrl-single,bits:
119        description: Register bit configuration for pinctrl-single,bit-per-mux
120        $ref: /schemas/types.yaml#/definitions/uint32-array
121        items:
122          - description: register offset
123          - description: value
124          - description: pin bitmask in the register
125
126      pinctrl-single,bias-pullup:
127        description: Optional bias pull up configuration
128        $ref: /schemas/types.yaml#/definitions/uint32-array
129        items:
130          - description: input
131          - description: enabled pull up bits
132          - description: disabled pull up bits
133          - description: bias pull up mask
134
135      pinctrl-single,bias-pulldown:
136        description: Optional bias pull down configuration
137        $ref: /schemas/types.yaml#/definitions/uint32-array
138        items:
139          - description: input
140          - description: enabled pull down bits
141          - description: disabled pull down bits
142          - description: bias pull down mask
143
144      pinctrl-single,drive-strength:
145        description: Optional drive strength configuration
146        $ref: /schemas/types.yaml#/definitions/uint32-array
147        items:
148          - description: drive strength current
149          - description: drive strength mask
150
151      pinctrl-single,input-schmitt:
152        description: Optional schmitt strength configuration
153        $ref: /schemas/types.yaml#/definitions/uint32-array
154        items:
155          - description: schmitt strength current
156          - description: schmitt strength mask
157
158      pinctrl-single,input-schmitt-enable:
159        description: Optional input schmitt configuration
160        $ref: /schemas/types.yaml#/definitions/uint32-array
161        items:
162          - description: input
163          - description: enable bits
164          - description: disable bits
165          - description: input schmitt mask
166
167      pinctrl-single,low-power-mode:
168        description: Optional low power mode configuration
169        $ref: /schemas/types.yaml#/definitions/uint32-array
170        items:
171          - description: low power mode value
172          - description: low power mode mask
173
174      pinctrl-single,slew-rate:
175        description: Optional slew rate configuration
176        $ref: /schemas/types.yaml#/definitions/uint32-array
177        items:
178          - description: slew rate
179          - description: slew rate mask
180
181allOf:
182  - $ref: pinctrl.yaml#
183
184required:
185  - compatible
186  - reg
187  - pinctrl-single,register-width
188
189additionalProperties: false
190
191examples:
192  - |
193    soc {
194      #address-cells = <1>;
195      #size-cells = <1>;
196
197      pinmux@4a100040 {
198        compatible = "pinctrl-single";
199        reg = <0x4a100040 0x0196>;
200        #address-cells = <1>;
201        #size-cells = <0>;
202        #pinctrl-cells = <2>;
203        #interrupt-cells = <1>;
204        interrupt-controller;
205        pinctrl-single,register-width = <16>;
206        pinctrl-single,function-mask = <0xffff>;
207        pinctrl-single,gpio-range = <&range 0 3 0>;
208        range: gpio-range {
209          #pinctrl-single,gpio-range-cells = <3>;
210        };
211
212        uart2-pins {
213          pinctrl-single,pins =
214            <0xd8 0x118>,
215            <0xda 0>,
216            <0xdc 0x118>,
217            <0xde 0>;
218        };
219      };
220    };