nxp,s32g2-siul2-pinctrl.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2# Copyright 2022 NXP
  3%YAML 1.2
  4---
  5$id: http://devicetree.org/schemas/pinctrl/nxp,s32g2-siul2-pinctrl.yaml#
  6$schema: http://devicetree.org/meta-schemas/core.yaml#
  7
  8title: NXP S32G2 pin controller
  9
 10maintainers:
 11  - Ghennadi Procopciuc <Ghennadi.Procopciuc@oss.nxp.com>
 12  - Chester Lin <chester62515@gmail.com>
 13
 14description: |
 15  S32G2 pinmux is implemented in SIUL2 (System Integration Unit Lite2),
 16  whose memory map is split into two regions:
 17    SIUL2_0 @ 0x4009c000
 18    SIUL2_1 @ 0x44010000
 19
 20  Every SIUL2 region has multiple register types, and here only MSCR and
 21  IMCR registers need to be revealed for kernel to configure pinmux.
 22
 23  Please note that some register indexes are reserved in S32G2, such as
 24  MSCR102-MSCR111, MSCR123-MSCR143, IMCR84-IMCR118 and IMCR398-IMCR429.
 25
 26properties:
 27  compatible:
 28    enum:
 29      - nxp,s32g2-siul2-pinctrl
 30
 31  reg:
 32    description: |
 33      A list of MSCR/IMCR register regions to be reserved.
 34      - MSCR (Multiplexed Signal Configuration Register)
 35        An MSCR register can configure the associated pin as either a GPIO pin
 36        or a function output pin depends on the selected signal source.
 37      - IMCR (Input Multiplexed Signal Configuration Register)
 38        An IMCR register can configure the associated pin as function input
 39        pin depends on the selected signal source.
 40    items:
 41      - description: MSCR registers group 0 in SIUL2_0
 42      - description: MSCR registers group 1 in SIUL2_1
 43      - description: MSCR registers group 2 in SIUL2_1
 44      - description: IMCR registers group 0 in SIUL2_0
 45      - description: IMCR registers group 1 in SIUL2_1
 46      - description: IMCR registers group 2 in SIUL2_1
 47
 48patternProperties:
 49  '-pins$':
 50    type: object
 51    additionalProperties: false
 52
 53    patternProperties:
 54      '-grp[0-9]$':
 55        type: object
 56        allOf:
 57          - $ref: pinmux-node.yaml#
 58          - $ref: pincfg-node.yaml#
 59        description: |
 60          Pinctrl node's client devices specify pin muxes using subnodes,
 61          which in turn use the standard properties below.
 62
 63        properties:
 64          bias-disable: true
 65          bias-high-impedance: true
 66          bias-pull-up: true
 67          bias-pull-down: true
 68          drive-open-drain: true
 69          input-enable: true
 70          output-enable: true
 71
 72          pinmux:
 73            description: |
 74              An integer array for representing pinmux configurations of
 75              a device. Each integer consists of a PIN_ID and a 4-bit
 76              selected signal source(SSS) as IOMUX setting, which is
 77              calculated as: pinmux = (PIN_ID << 4 | SSS)
 78
 79          slew-rate:
 80            description: Supported slew rate based on Fmax values (MHz)
 81            enum: [83, 133, 150, 166, 208]
 82
 83        additionalProperties: false
 84
 85required:
 86  - compatible
 87  - reg
 88
 89additionalProperties: false
 90
 91examples:
 92  - |
 93    pinctrl@4009c240 {
 94        compatible = "nxp,s32g2-siul2-pinctrl";
 95
 96              /* MSCR0-MSCR101 registers on siul2_0 */
 97        reg = <0x4009c240 0x198>,
 98              /* MSCR112-MSCR122 registers on siul2_1 */
 99              <0x44010400 0x2c>,
100              /* MSCR144-MSCR190 registers on siul2_1 */
101              <0x44010480 0xbc>,
102              /* IMCR0-IMCR83 registers on siul2_0 */
103              <0x4009ca40 0x150>,
104              /* IMCR119-IMCR397 registers on siul2_1 */
105              <0x44010c1c 0x45c>,
106              /* IMCR430-IMCR495 registers on siul2_1 */
107              <0x440110f8 0x108>;
108
109        llce-can0-pins {
110            llce-can0-grp0 {
111                pinmux = <0x2b0>;
112                input-enable;
113                slew-rate = <208>;
114            };
115
116            llce-can0-grp1 {
117                pinmux = <0x2c2>;
118                output-enable;
119                slew-rate = <208>;
120            };
121        };
122    };
123...