nvidia,tegra210-pinmux.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra210-pinmux.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: NVIDIA Tegra210 Pinmux Controller
  8
  9maintainers:
 10  - Thierry Reding <thierry.reding@gmail.com>
 11  - Jon Hunter <jonathanh@nvidia.com>
 12
 13properties:
 14  compatible:
 15    const: nvidia,tegra210-pinmux
 16
 17  reg:
 18    items:
 19      - description: APB_MISC_GP_*_PADCTRL register (pad control)
 20      - description: PINMUX_AUX_* registers (pinmux)
 21
 22patternProperties:
 23  "^pinmux(-[a-z0-9-_]+)?$":
 24    type: object
 25
 26    # pin groups
 27    additionalProperties:
 28      $ref: nvidia,tegra-pinmux-common.yaml
 29      additionalProperties: false
 30      properties:
 31        nvidia,pins:
 32          items:
 33            enum: [ als_prox_int_px3, ap_ready_pv5, ap_wake_bt_ph3,
 34                    ap_wake_nfc_ph7, aud_mclk_pbb0, batt_bcl, bt_rst_ph4,
 35                    bt_wake_ap_ph5, button_home_py1, button_power_on_px5,
 36                    button_slide_sw_py0, button_vol_down_px7,
 37                    button_vol_up_px6, cam1_mclk_ps0, cam1_pwdn_ps7,
 38                    cam1_strobe_pt1, cam2_mclk_ps1, cam2_pwdn_pt0,
 39                    cam_af_en_ps5, cam_flash_en_ps6, cam_i2c_scl_ps2,
 40                    cam_i2c_sda_ps3, cam_rst_ps4, clk_32k_in, clk_32k_out_py5,
 41                    clk_req, core_pwr_req, cpu_pwr_req, dap1_din_pb1,
 42                    dap1_dout_pb2, dap1_fs_pb0, dap1_sclk_pb3, dap2_din_paa2,
 43                    dap2_dout_paa3, dap2_fs_paa0, dap2_sclk_paa1, dap4_din_pj5,
 44                    dap4_dout_pj6, dap4_fs_pj4, dap4_sclk_pj7, dmic1_clk_pe0,
 45                    dmic1_dat_pe1, dmic2_clk_pe2, dmic2_dat_pe3, dmic3_clk_pe4,
 46                    dmic3_dat_pe5, dp_hpd0_pcc6, dvfs_clk_pbb2, dvfs_pwm_pbb1,
 47                    gen1_i2c_scl_pj1, gen1_i2c_sda_pj0, gen2_i2c_scl_pj2,
 48                    gen2_i2c_sda_pj3, gen3_i2c_scl_pf0, gen3_i2c_sda_pf1,
 49                    gpio_x1_aud_pbb3, gpio_x3_aud_pbb4, gps_en_pi2,
 50                    gps_rst_pi3, hdmi_cec_pcc0, hdmi_int_dp_hpd_pcc1,
 51                    jtag_rtck, lcd_bl_en_pv1, lcd_bl_pwm_pv0, lcd_gpio1_pv3,
 52                    lcd_gpio2_pv4, lcd_rst_pv2, lcd_te_py2, modem_wake_ap_px0,
 53                    motion_int_px2, nfc_en_pi0, nfc_int_pi1, pa6, pcc7, pe6,
 54                    pe7, pex_l0_clkreq_n_pa1, pex_l0_rst_n_pa0,
 55                    pex_l1_clkreq_n_pa4, pex_l1_rst_n_pa3, pex_wake_n_pa2, ph6,
 56                    pk0, pk1, pk2, pk3, pk4, pk5, pk6, pk7, pl0, pl1,
 57                    pwr_i2c_scl_py3, pwr_i2c_sda_py4, pwr_int_n, pz0, pz1, pz2,
 58                    pz3, pz4, pz5, qspi_cs_n_pee1, qspi_io0_pee2,
 59                    qspi_io1_pee3, qspi_io2_pee4, qspi_io3_pee5, qspi_sck_pee0,
 60                    sata_led_active_pa5, sdmmc1_clk_pm0, sdmmc1_cmd_pm1,
 61                    sdmmc1_dat0_pm5, sdmmc1_dat1_pm4, sdmmc1_dat2_pm3,
 62                    sdmmc1_dat3_pm2, sdmmc3_clk_pp0, sdmmc3_cmd_pp1,
 63                    sdmmc3_dat0_pp5, sdmmc3_dat1_pp4, sdmmc3_dat2_pp3,
 64                    sdmmc3_dat3_pp2, shutdown, spdif_in_pcc3, spdif_out_pcc2,
 65                    spi1_cs0_pc3, spi1_cs1_pc4, spi1_miso_pc1, spi1_mosi_pc0,
 66                    spi1_sck_pc2, spi2_cs0_pb7, spi2_cs1_pdd0, spi2_miso_pb5,
 67                    spi2_mosi_pb4, spi2_sck_pb6, spi4_cs0_pc6, spi4_miso_pd0,
 68                    spi4_mosi_pc7, spi4_sck_pc5, temp_alert_px4, touch_clk_pv7,
 69                    touch_int_px1, touch_rst_pv6, uart1_cts_pu3, uart1_rts_pu2,
 70                    uart1_rx_pu1, uart1_tx_pu0, uart2_cts_pg3, uart2_rts_pg2,
 71                    uart2_rx_pg1, uart2_tx_pg0, uart3_cts_pd4, uart3_rts_pd3,
 72                    uart3_rx_pd2, uart3_tx_pd1, uart4_cts_pi7, uart4_rts_pi6,
 73                    uart4_rx_pi5, uart4_tx_pi4, usb_vbus_en0_pcc4,
 74                    usb_vbus_en1_pcc5, wifi_en_ph0, wifi_rst_ph1,
 75                    wifi_wake_ap_ph2,
 76                    # drive groups
 77                    drive_pa6, drive_pcc7, drive_pe6, drive_pe7, drive_ph6,
 78                    drive_pk0, drive_pk1, drive_pk2, drive_pk3, drive_pk4,
 79                    drive_pk5, drive_pk6, drive_pk7, drive_pl0, drive_pl1,
 80                    drive_pz0, drive_pz1, drive_pz2, drive_pz3, drive_pz4,
 81                    drive_pz5, drive_sdmmc1, drive_sdmmc2, drive_sdmmc3,
 82                    drive_sdmmc4 ]
 83
 84        nvidia,function:
 85          enum: [ aud, bcl, blink, ccla, cec, cldvfs, clk, core, cpu, displaya,
 86                  displayb, dmic1, dmic2, dmic3, dp, dtv, extperiph3, i2c1,
 87                  i2c2, i2c3, i2cpmu, i2cvi, i2s1, i2s2, i2s3, i2s4a, i2s4b,
 88                  i2s5a, i2s5b, iqc0, iqc1, jtag, pe, pe0, pe1, pmi, pwm0,
 89                  pwm1, pwm2, pwm3, qspi, rsvd0, rsvd1, rsvd2, rsvd3, sata,
 90                  sdmmc1, sdmmc3, shutdown, soc, sor0, sor1, spdif, spi1, spi2,
 91                  spi3, spi4, sys, touch, uart, uarta, uartb, uartc, uartd,
 92                  usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, vimclk, vimclk2 ]
 93
 94        nvidia,pull: true
 95        nvidia,tristate: true
 96        nvidia,pull-down-strength: true
 97        nvidia,pull-up-strength: true
 98        nvidia,high-speed-mode: true
 99        nvidia,enable-input: true
100        nvidia,open-drain: true
101        nvidia,lock: true
102        nvidia,drive-type: true
103        nvidia,io-hv: true
104        nvidia,slew-rate-rising: true
105        nvidia,slew-rate-falling: true
106
107      required:
108        - nvidia,pins
109
110additionalProperties: false
111
112required:
113  - compatible
114  - reg
115
116examples:
117  - |
118    #include <dt-bindings/pinctrl/pinctrl-tegra.h>
119
120    pinmux: pinmux@70000800 {
121        compatible = "nvidia,tegra210-pinmux";
122        reg = <0x700008d4 0x02a8>, /* Pad control registers */
123              <0x70003000 0x1000>; /* Mux registers */
124
125        pinctrl-names = "boot";
126        pinctrl-0 = <&state_boot>;
127
128        state_boot: pinmux {
129            gen1_i2c_scl_pj1 {
130                nvidia,pins = "gen1_i2c_scl_pj1";
131                nvidia,function = "i2c1";
132                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
133                nvidia,tristate = <TEGRA_PIN_DISABLE>;
134                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
135                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
136                nvidia,io-hv = <TEGRA_PIN_ENABLE>;
137            };
138        };
139    };
140...