mediatek,mt65xx-pinctrl.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: MediaTek MT65xx Pin Controller
  8
  9maintainers:
 10  - Sean Wang <sean.wang@kernel.org>
 11
 12description:
 13  The MediaTek's MT65xx Pin controller is used to control SoC pins.
 14
 15properties:
 16  compatible:
 17    enum:
 18      - mediatek,mt2701-pinctrl
 19      - mediatek,mt2712-pinctrl
 20      - mediatek,mt6397-pinctrl
 21      - mediatek,mt7623-pinctrl
 22      - mediatek,mt8127-pinctrl
 23      - mediatek,mt8135-pinctrl
 24      - mediatek,mt8167-pinctrl
 25      - mediatek,mt8173-pinctrl
 26      - mediatek,mt8516-pinctrl
 27
 28  reg:
 29    maxItems: 1
 30
 31  pins-are-numbered:
 32    $ref: /schemas/types.yaml#/definitions/flag
 33    description:
 34      Specify the subnodes are using numbered pinmux to specify pins. (UNUSED)
 35    deprecated: true
 36
 37  gpio-controller: true
 38
 39  "#gpio-cells":
 40    const: 2
 41    description:
 42      Number of cells in GPIO specifier. Since the generic GPIO binding is used,
 43      the amount of cells must be specified as 2. See the below mentioned gpio
 44      binding representation for description of particular cells.
 45
 46  gpio-line-names: true
 47
 48  mediatek,pctl-regmap:
 49    $ref: /schemas/types.yaml#/definitions/phandle-array
 50    items:
 51      maxItems: 1
 52    minItems: 1
 53    maxItems: 2
 54    description:
 55      Should be phandles of the syscfg node.
 56
 57  interrupt-controller: true
 58
 59  interrupts:
 60    minItems: 1
 61    maxItems: 3
 62
 63  "#interrupt-cells":
 64    const: 2
 65
 66required:
 67  - compatible
 68  - gpio-controller
 69  - "#gpio-cells"
 70
 71allOf:
 72  - $ref: pinctrl.yaml#
 73
 74patternProperties:
 75  'pins$':
 76    type: object
 77    additionalProperties: false
 78    patternProperties:
 79      '(^pins|pins?$)':
 80        type: object
 81        additionalProperties: false
 82        description:
 83          A pinctrl node should contain at least one subnodes representing the
 84          pinctrl groups available on the machine. Each subnode will list the
 85          pins it needs, and how they should be configured, with regard to muxer
 86          configuration, pullups, drive strength, input enable/disable and input
 87          schmitt.
 88        $ref: /schemas/pinctrl/pincfg-node.yaml
 89
 90        properties:
 91          pinmux:
 92            description:
 93              Integer array, represents gpio pin number and mux setting.
 94              Supported pin number and mux varies for different SoCs, and are
 95              defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
 96
 97          bias-disable: true
 98
 99          bias-pull-up:
100            description:
101              Besides generic pinconfig options, it can be used as the pull up
102              settings for 2 pull resistors, R0 and R1. User can configure those
103              special pins. Some macros have been defined for this usage, such
104              as MTK_PUPD_SET_R1R0_00. See dt-bindings/pinctrl/mt65xx.h for
105              valid arguments.
106
107          bias-pull-down: true
108
109          input-enable: true
110
111          input-disable: true
112
113          output-low: true
114
115          output-high: true
116
117          input-schmitt-enable: true
118
119          input-schmitt-disable: true
120
121          drive-strength:
122            description:
123              Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA,
124              etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments.
125
126        required:
127          - pinmux
128
129additionalProperties: false
130
131examples:
132  - |
133    #include <dt-bindings/interrupt-controller/irq.h>
134    #include <dt-bindings/interrupt-controller/arm-gic.h>
135    #include <dt-bindings/pinctrl/mt8135-pinfunc.h>
136
137    soc {
138        #address-cells = <2>;
139        #size-cells = <2>;
140
141        pinctrl@1c20800 {
142            compatible = "mediatek,mt8135-pinctrl";
143            reg = <0 0x1000B000 0 0x1000>;
144            mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
145            gpio-controller;
146            #gpio-cells = <2>;
147            interrupt-controller;
148            #interrupt-cells = <2>;
149            interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
150                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
151                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
152
153            i2c0_pins_a: i2c0-pins {
154                pins1 {
155                    pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
156                             <MT8135_PIN_101_SCL0__FUNC_SCL0>;
157                    bias-disable;
158                };
159            };
160
161            i2c1_pins_a: i2c1-pins {
162                pins {
163                    pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
164                             <MT8135_PIN_196_SCL1__FUNC_SCL1>;
165                    bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
166                };
167            };
168
169            i2c2_pins_a: i2c2-pins {
170                pins1 {
171                    pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
172                    bias-pull-down;
173                };
174
175                pins2 {
176                    pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
177                    bias-pull-up;
178                };
179            };
180        };
181    };