marvell,armada3710-xb-pinctrl.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pinctrl/marvell,armada3710-xb-pinctrl.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Marvell Armada 37xx SoC pin and gpio controller
  8
  9maintainers:
 10  - Gregory CLEMENT <gregory.clement@bootlin.com>
 11  - Marek Behún <kabel@kernel.org>
 12  - Miquel Raynal <miquel.raynal@bootlin.com>
 13
 14description: >
 15  Each Armada 37xx SoC come with two pin and gpio controller one for the south
 16  bridge and the other for the north bridge.
 17
 18  Inside this set of register the gpio latch allows exposing some configuration
 19  of the SoC and especially the clock frequency of the xtal. Hence, this node is
 20  a represent as syscon allowing sharing the register between multiple hardware
 21  block.
 22
 23properties:
 24  compatible:
 25    items:
 26      - enum:
 27          - marvell,armada3710-sb-pinctrl
 28          - marvell,armada3710-nb-pinctrl
 29      - const: syscon
 30      - const: simple-mfd
 31
 32  reg:
 33    items:
 34      - description: pinctrl and GPIO controller registers
 35      - description: interrupt controller registers
 36
 37  gpio:
 38    description: GPIO controller subnode
 39    type: object
 40    additionalProperties: false
 41
 42    properties:
 43      '#gpio-cells':
 44        const: 2
 45
 46      gpio-controller: true
 47
 48      gpio-ranges:
 49        description: Range of pins managed by the GPIO controller
 50
 51      '#interrupt-cells':
 52        const: 2
 53
 54      interrupt-controller: true
 55
 56      interrupts:
 57        description: List of interrupt specifiers for the GPIO controller
 58
 59    required:
 60      - '#gpio-cells'
 61      - gpio-ranges
 62      - gpio-controller
 63      - '#interrupt-cells'
 64      - interrupt-controller
 65      - interrupts
 66
 67  xtal-clk:
 68    type: object
 69    additionalProperties: false
 70
 71    properties:
 72      compatible:
 73        const: marvell,armada-3700-xtal-clock
 74
 75      '#clock-cells':
 76        const: 0
 77
 78      clock-output-names: true
 79
 80patternProperties:
 81  '-pins$':
 82    $ref: pinmux-node.yaml#
 83    additionalProperties: false
 84
 85    properties:
 86      groups:
 87        enum: [ emmc_nb, i2c1, i2c2, jtag, mii_col, onewire, pcie1,
 88                pcie1_clkreq, pcie1_wakeup, pmic0, pmic1, ptp, ptp_clk,
 89                ptp_trig, pwm0, pwm1, pwm2, pwm3, rgmii, sdio0, sdio_sb, smi,
 90                spi_cs1, spi_cs2, spi_cs3, spi_quad, uart1, uart2,
 91                usb2_drvvbus1, usb32_drvvbus0 ]
 92
 93      function:
 94        enum: [ drvbus, emmc, gpio, i2c, jtag, led, mii, mii_err, onewire,
 95                pcie, pmic, ptp, pwm, sdio, smi, spi, uart ]
 96
 97required:
 98  - compatible
 99  - reg
100
101additionalProperties: false
102
103examples:
104  - |
105    #include <dt-bindings/interrupt-controller/arm-gic.h>
106
107    pinctrl_sb: pinctrl@18800 {
108        compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd";
109        reg = <0x18800 0x100>, <0x18C00 0x20>;
110
111        gpio {
112            #gpio-cells = <2>;
113            gpio-ranges = <&pinctrl_sb 0 0 29>;
114            gpio-controller;
115            #interrupt-cells = <2>;
116            interrupt-controller;
117            interrupts =
118                <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
119                <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
120                <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
121                <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
122                <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
123        };
124    };